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AIP74HC00TA14.TR
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Wuxi I-core Elec Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAIP74HC00TA14.TR
Wuxi I-core Elec · Logic Gates · TSSOP-14
AIP74HC00TA14.TR from Wuxi I-core Elec, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A of NAND gate 1; the recommended input voltage range is 0 V to VCC and the input clamp current limit is ±20 mA. |
| 2 | 1B | input | Data input B of NAND gate 1; the recommended input voltage range is 0 V to VCC and the input clamp current limit is ±20 mA. |
| 3 | 1Y | output | Output of NAND gate 1 (1Y = NOT(1A AND 1B)); it goes high when either input is low. |
| 4 | 2A | input | Data input A of NAND gate 2; the recommended input voltage range is 0 V to VCC and the input clamp current limit is ±20 mA. |
| 5 | 2B | input | Data input B of NAND gate 2; the recommended input voltage range is 0 V to VCC and the input clamp current limit is ±20 mA. |
| 6 | 2Y | output | Output of NAND gate 2 (2Y = NOT(2A AND 2B)); it goes high when either input is low. |
| 7 | GND | power_in | Ground reference (0 V) for the device. |
| 8 | 3Y | output | Output of NAND gate 3 (3Y = NOT(3A AND 3B)); it goes high when either input is low. |
| 9 | 3A | input | Data input A of NAND gate 3; the recommended input voltage range is 0 V to VCC and the input clamp current limit is ±20 mA. |
| 10 | 3B | input | Data input B of NAND gate 3; the recommended input voltage range is 0 V to VCC and the input clamp current limit is ±20 mA. |
| 11 | 4Y | output | Output of NAND gate 4 (4Y = NOT(4A AND 4B)); it goes high when either input is low. |
| 12 | 4A | input | Data input A of NAND gate 4; the recommended input voltage range is 0 V to VCC and the input clamp current limit is ±20 mA. |
| 13 | 4B | input | Data input B of NAND gate 4; the recommended input voltage range is 0 V to VCC and the input clamp current limit is ±20 mA. |
| 14 | VCC | power_in | Supply voltage; the AiP74HC00 recommended range is 2.0 V to 6.0 V, absolute maximum is -0.5 V to +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I-core Elec |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 7 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V或VI>VCC+0.5V | 7 | |
| Output current | IO | -25 | 25 | mA | -0.5V<VO<VCC+0.5V | 7 | |
| Supply current | ICC | 50 | mA | 7 | |||
| Total power dissipation | Ptot | 500 | mW | 7 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 7 | ||
| Soldering temperature | TL | 260 | ℃ | 10秒; SOP/TSSOP package | 7 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 7 | |
| Input rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 7 | ||
| Input rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 7 | |
| Input rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 7 | ||
| Operating ambient temperature | Tamb | -40 | 125 | ℃ | 7 | ||
| High-level input voltage | VIH | 1.5 | V | Tamb=-40~+85℃; VCC=2.0V | 9 | ||
| High-level input voltage | VIH | 3.15 | V | Tamb=-40~+85℃; VCC=4.5V | 9 | ||
| High-level input voltage | VIH | 4.2 | V | Tamb=-40~+85℃; VCC=6.0V | 9 | ||
| Low-level input voltage | VIL | 0.5 | V | Tamb=-40~+85℃; VCC=2.0V | 9 | ||
| Low-level input voltage | VIL | 1.35 | V | Tamb=-40~+85℃; VCC=4.5V | 9 | ||
| Low-level input voltage | VIL | 1.8 | V | Tamb=-40~+85℃; VCC=6.0V | 9 | ||
| High-level output voltage | VOH | 1.9 | V | Tamb=-40~+85℃; VI=VIH或VIL; IO=-20uA; VCC=2.0V | 9 | ||
| High-level output voltage | VOH | 4.4 | V | Tamb=-40~+85℃; VI=VIH或VIL; IO=-20uA; VCC=4.5V | 9 | ||
| High-level output voltage | VOH | 5.9 | V | Tamb=-40~+85℃; VI=VIH或VIL; IO=-20uA; VCC=6.0V | 9 | ||
| High-level output voltage | VOH | 3.84 | V | Tamb=-40~+85℃; VI=VIH或VIL; IO=-4.0mA; VCC=4.5V | 9 | ||
| High-level output voltage | VOH | 5.34 | V | Tamb=-40~+85℃; VI=VIH或VIL; IO=-5.2mA; VCC=6.0V | 9 | ||
| Low-level output voltage | VOL | 0.1 | V | Tamb=-40~+85℃; VI=VIH或VIL; IO=20uA; VCC=2.0V | 9 | ||
| Low-level output voltage | VOL | 0.33 | V | Tamb=-40~+85℃; VI=VIH或VIL; IO=4.0mA; VCC=4.5V | 9 | ||
| Input leakage current | II | -1 | 1 | uA | Tamb=-40~+85℃; VI=VCC或GND; VCC=6.0V | 9 | |
| Quiescent supply current | ICC | 20 | uA | Tamb=-40~+85℃; VI=VCC或GND; IO=0A; VCC=6.0V | 9 | ||
| High-level input voltage | VIH | 1.5 | V | Tamb=-40~+125℃; VCC=2.0V | 10 | ||
| High-level input voltage | VIH | 3.15 | V | Tamb=-40~+125℃; VCC=4.5V | 10 | ||
| High-level input voltage | VIH | 4.2 | V | Tamb=-40~+125℃; VCC=6.0V | 10 | ||
| Low-level input voltage | VIL | 0.5 | V | Tamb=-40~+125℃; VCC=2.0V | 10 | ||
| Low-level input voltage | VIL | 1.35 | V | Tamb=-40~+125℃; VCC=4.5V | 10 | ||
| Low-level input voltage | VIL | 1.8 | V | Tamb=-40~+125℃; VCC=6.0V | 10 | ||
| High-level output voltage | VOH | 1.9 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-20uA; VCC=2.0V | 10 | ||
| High-level output voltage | VOH | 4.4 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-20uA; VCC=4.5V | 10 | ||
| High-level output voltage | VOH | 5.9 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-20uA; VCC=6.0V | 10 | ||
| High-level output voltage | VOH | 3.7 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-4.0mA; VCC=4.5V | 10 | ||
| High-level output voltage | VOH | 5.2 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=-5.2mA; VCC=6.0V | 10 | ||
| Low-level output voltage | VOL | 0.1 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=20uA; VCC=2.0V | 10 | ||
| Low-level output voltage | VOL | 0.4 | V | Tamb=-40~+125℃; VI=VIH或VIL; IO=4.0mA; VCC=4.5V | 10 | ||
| Input leakage current | II | -1 | 1 | uA | Tamb=-40~+125℃; VI=VCC或GND; VCC=6.0V | 10 | |
| Quiescent supply current | ICC | 40 | uA | Tamb=-40~+125℃; VI=VCC或GND; IO=0A; VCC=6.0V | 10 | ||
| Propagation delay nA, nB to nY | tpd | 115 | ns | Tamb=-40~+85℃; VCC=2.0V | 12 | ||
| Propagation delay nA, nB to nY | tpd | 23 | ns | Tamb=-40~+85℃; VCC=4.5V | 12 | ||
| Propagation delay nA, nB to nY | tpd | 20 | ns | Tamb=-40~+85℃; VCC=6.0V | 12 | ||
| Output transition time | tt | 95 | ns | Tamb=-40~+85℃; VCC=2.0V | 12 | ||
| Output transition time | tt | 19 | ns | Tamb=-40~+85℃; VCC=4.5V | 12 | ||
| Output transition time | tt | 16 | ns | Tamb=-40~+85℃; VCC=6.0V | 12 | ||
| Propagation delay nA, nB to nY | tpd | 135 | ns | Tamb=-40~+125℃; VCC=2.0V | 12 | ||
| Propagation delay nA, nB to nY | tpd | 27 | ns | Tamb=-40~+125℃; VCC=4.5V | 12 | ||
| Output transition time | tt | 110 | ns | Tamb=-40~+125℃; VCC=2.0V | 12 | ||
| Output transition time | tt | 22 | ns | Tamb=-40~+125℃; VCC=4.5V | 12 |
CAD (KiCad official)
- Symbol:
AIP74HC00TA14.TR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
aip74hc00ta14-tr-etched.step/aip74hc00ta14-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip74hc00ta14-tr.step/aip74hc00ta14-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I-core Elec datasheet (18 pp, sha256
6486d44f32d31aa8, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).