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AIP1638
Public Made by Adomby adom
Wuxi I-core Elec LED Display Drivers, SOP-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAIP1638
Wuxi I-core Elec · LED Display Drivers · SOP-28-300mil
AIP1638 from Wuxi I-core Elec, in a SOP-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K1 | input | Key-scan data input whose data is latched at the end of the display cycle; has 10kΩ internal pull-down. |
| 2 | K2 | input | Key-scan data input whose data is latched at the end of the display cycle; has 10kΩ internal pull-down. |
| 3 | K3 | input | Key-scan data input whose data is latched at the end of the display cycle; has 10kΩ internal pull-down. |
| 4 | VDD | power_in | Logic supply, 5V±10% (recommended 3 to 5.5V). |
| 5 | SEG1/KS1 | output | Segment 1 output, P-channel open-drain (connect to LED anode), also used as key-scan line KS1. |
| 6 | SEG2/KS2 | output | Segment 2 output, P-channel open-drain (connect to LED anode), also used as key-scan line KS2. |
| 7 | SEG3/KS3 | output | Segment 3 output, P-channel open-drain (connect to LED anode), also used as key-scan line KS3. |
| 8 | SEG4/KS4 | output | Segment 4 output, P-channel open-drain (connect to LED anode), also used as key-scan line KS4. |
| 9 | SEG5/KS5 | output | Segment 5 output, P-channel open-drain (connect to LED anode), also used as key-scan line KS5. |
| 10 | SEG6/KS6 | output | Segment 6 output, P-channel open-drain (connect to LED anode), also used as key-scan line KS6. |
| 11 | SEG7/KS7 | output | Segment 7 output, P-channel open-drain (connect to LED anode), also used as key-scan line KS7. |
| 12 | SEG8/KS8 | output | Segment 8 output, P-channel open-drain (connect to LED anode), also used as key-scan line KS8. |
| 13 | SEG9 | output | Segment 9 output, P-channel open-drain (connect to LED anode). |
| 14 | SEG10 | output | Segment 10 output, P-channel open-drain (connect to LED anode). |
| 15 | VDD | power_in | Logic supply, 5V±10% (recommended 3 to 5.5V). |
| 16 | GR7 | output | Grid 7 digit output, N-channel open-drain (connect to LED cathode). |
| 17 | GR8 | output | Grid 8 digit output, N-channel open-drain (connect to LED cathode). |
| 18 | GND | power_in | Logic ground, connect to system ground. |
| 19 | GR1 | output | Grid 1 digit output, N-channel open-drain (connect to LED cathode). |
| 20 | GR2 | output | Grid 2 digit output, N-channel open-drain (connect to LED cathode). |
| 21 | GR3 | output | Grid 3 digit output, N-channel open-drain (connect to LED cathode). |
| 22 | GR4 | output | Grid 4 digit output, N-channel open-drain (connect to LED cathode). |
| 23 | GR5 | output | Grid 5 digit output, N-channel open-drain (connect to LED cathode). |
| 24 | GR6 | output | Grid 6 digit output, N-channel open-drain (connect to LED cathode). |
| 25 | GND | power_in | Logic ground, connect to system ground. |
| 26 | DIO | bidirectional | Serial data input/output on CLK rising edge, LSB first; N-channel open-drain output needing an external 1k-10k pull-up (10k recommended) when reading keys. |
| 27 | CLK | input | Clock input; serial data is input/output on the rising edge. |
| 28 | STB | input | Chip select that initializes the serial interface on rising or falling edge; first byte after STB low is the command, and CLK is ignored when STB is high. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I-core Elec |
| Package | SOP-28-300mil |
| Category | Display Modules / LED Drivers / Display Drivers |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic supply voltage | VDD | -0.5 | 7 | V | GND=0V, Tamb=25°C | 4 | |
| Logic input voltage | VTI | -0.5 | 5.5 | V | -0.5 to VDD+0.5 V | 4 | |
| LED SEG drive output current | IO1 | -50 | mA | 4 | |||
| LED GR drive output current | IO2 | 200 | mA | 4 | |||
| Power dissipation | PD | 400 | mW | 4 | |||
| Operating ambient temperature | Tamb | -40 | 85 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Soldering temperature | TL | 250 | °C | 10 s | 4 | ||
| Logic supply voltage | VDD | 3 | 5 | 5.5 | V | Tamb=-20~+70°C, GND=0V | 4 |
| High-level input voltage | VIH | 0.7 | V | min 0.7VDD, max VDD | 4 | ||
| Low-level input voltage | VIL | 0 | 0.3 | V | max 0.3VDD | 4 | |
| High-level output current | IOH1 | -20 | -25 | -40 | mA | SEG1 |
4 |
| High-level output current | IOH2 | -20 | -30 | -50 | mA | SEG1~SEG10, Vo = VDD-3V | 4 |
| Low-level output current | IOL1 | 80 | 140 | mA | GR1~GR8, Vo=0.3V | 4 | |
| Low-level output current (DIO) | Idout | 4 | mA | VO = 0.4V, dout | 4 | ||
| High-level output current tolerance | Itolsg | 5 | % | VO = VDD-3V, SEG1~SEG10 | 4 | ||
| Output pull-down resistance | RL | 10 | kΩ | K1~K3 | 4 | ||
| Input current | II | -1 | 1 | µA | VI=VDD/GND | 4 | |
| High-level input voltage | VIH | 0.7 | V | CLK, DIO, STB; min 0.7VDD | 4 | ||
| Low-level input voltage | VIL | 0.3 | V | CLK, DIO, STB; max 0.3VDD | 4 | ||
| Hysteresis voltage | VH | 0.35 | V | CLK, DIO, STB | 4 | ||
| Dynamic supply current | IDDdyn | 5 | mA | no load, display off | 4 | ||
| Oscillation frequency | Fosc | 400 | kHz | Tamb=-20~+70°C, VDD=4.5~5.5V | 5 | ||
| Oscillation frequency tolerance | Fosc | -5 | 5 | % | built-in RC oscillator 400KHz±5% | 2 | |
| Propagation delay time | Tplz | 300 | ns | CLK→DIO, CL=15pF, RL=10kΩ | 5 | ||
| Propagation delay time | Tpzl | 100 | ns | CLK→DIO, CL=15pF, RL=10kΩ | 5 | ||
| Rise time SEG | TTZH1 | 2 | µs | SEG1~SEG10, CL=300pF | 5 | ||
| Rise time GR | TTZH2 | 0.5 | µs | GR1~GR8, CL=300pF | 5 | ||
| Fall time | TTHZ | 120 | µs | CL=300pF, SEGN, GRN | 5 | ||
| Maximum clock frequency | Fmax | 1 | MHz | duty cycle 50% | 5 | ||
| Input capacitance | CI | 15 | pF | 5 | |||
| Clock pulse width | PWCLK | 400 | ns | 5 | |||
| Strobe pulse width | PWSTB | 1 | µs | 5 | |||
| Data setup time | tSETUP | 100 | ns | 5 | |||
| Data hold time | tHOLD | 100 | ns | 5 | |||
| CLK→STB time | tCLK | 1 | µs | CLK↑→STB↑ | 5 | ||
| Wait time | tWAIT | 1 | µs | CLK↑→CLK↓ | 5 |
CAD (KiCad official)
- Symbol:
AIP1638 - Footprint:
Package_SO:SOP-28_8.4x18.16mm_P1.27mm - 3D model: SOP-28-300mil (KiCad packages3D, STEP)
- 3D model files:
aip1638-etched.step/aip1638-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip1638.step/aip1638.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I-core Elec datasheet (17 pp, sha256
7a29285e47b59992, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).