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AI Flow: Reverse Engineering
Public Made by Adomby adom
Photos of a PCB to a tagged KiCad copy: parts placed, copper and nets with their evidence, a schematic, a measured confidence score, bench tests and a video of the run.
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Caleb
Version 0.3.0: new copper reader, dome via filter, every layer read from the photos, net evidence, measured confidence;…
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This is a three phase motor controller. A power connector, a bank of
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capacitors, six MOSFETs.
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A gate driver and a microcontroller in the middle, each turned 45 degrees.
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We have no design files in this flow. Just four photos.
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Turn it over, and the copper shows through the solder mask.
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Pours, fine tracks, gaps between them, and more than a thousand tiny domes
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where vias push up through the mask.
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Everything from here on is read from pictures like these.
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The job: find the parts and the blocks. Copy all the copper. Work out what
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can't be seen, propose a layer count, say how sure you are, and list the tests
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that would settle the rest.
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Then a harder bar. Put every piece of copper on a net. Make the layers match
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the photos. And keep going until confidence measures 90%, or say why it can't.
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This is AI Flow: Reverse Engineering. A Rust program does the measuring, and
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an AI supplies the judgment, like what a part is called.
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11 steps, from intake to report. Each one has a check that has to pass, and
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each one gets recorded.
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First, the photos. It finds the board edge in each one and straightens it.
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The bottom gets turned over and pinned to the top through 40 holes that both
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sides share.
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With one hole held out each time, they land within about 0.03 mm.
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Scale comes from the board itself. Header rows have standard pitches, 2 mm and
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2.54 mm.
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The driver chip's 6 mm body confirms which standard they are. That gives 46.6
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pixels per millimeter.
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Next, the parts. 137 of them, and 103 get placed by their own pads.
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Markings get read where they're legible, like this TI DRV8323S.
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Most small ceramics carry no marking at all, so their values just aren't in
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the photos. The flow says so, and doesn't guess.
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Silkscreen and circuit role sort them into 11 blocks.
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Power entry, the power stage, sensing, the logic supply, the gate driver and
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the microcontroller. Then CAN, AUX, the fan, motor temperature and the
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mounting holes.
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Now the hard part. Under solder mask, copper looks a little lighter than bare
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laminate, and thin dark lines mark the gaps.
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The reader follows those gaps, and the board comes apart into islands.
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Here's the published version next to this one. Fine tracks that used to be
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missing now come through.
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That's 828 pours and 2,588 tracks.
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Looking closely found a real defect. The dark side of each dome was being cut
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out of solid pours.
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So the reader learned what a dome's shadow looks like, and now those pours
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read solid. Domes with a hole beside them dropped from 396 to 68.
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Vias get a shading test. A real dome is lit on one side and shadowed on the
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other, in the same direction as all the rest.
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The published filter ringed silkscreen and missed most of the domes. The new
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one sits on them.
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1,329 kept. The top face shows none it can trust, so these all come from the
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bottom. A few are still missed along the edges.
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It doesn't stop at copper. Each pixel gets sorted by material: mask,
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silkscreen, metal, or a part sitting on top.
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Silkscreen, mask openings, exposed metal, holes and the outline all get read
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from the photos, then written into their own KiCad layers.
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All of it goes into a real KiCad project, as photographed, before anything
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gets guessed. Here it is over the top photo, and over the bottom.
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Every stage opens as an interactive board. Pick a net and all of it lights up:
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ground, the input rail, a phase.
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Then a separate check compares what KiCad draws with what the photos show, on
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tiles the reader wasn't tuned on.
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Green agrees. Red is drawn but not seen. Blue is seen but not drawn. Purple is
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hidden under a part, so it isn't scored.
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The bottom scores 0.87. The top, 0.82, on only about half the board, because
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parts cover the rest.
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Next, every piece of copper gets a net, and a record of how it got it. Pieces
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get stitched into conductors wherever no gap separates them.
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Green means a pad touches it. Blue, it's joined through a via. Yellow is
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inferred, orange only by group. Red has no net.
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Three quarters of the copper area now has direct evidence. But 47% of track
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length is still red, so that goal isn't met.
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A schematic comes out too. All 77 nets are still marked inferred.
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Now the connections nobody can see. The flow has its own router, and it uses
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every inner layer.
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Real vias pass through pours, so crossing copper from the photos is expensive,
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not forbidden. And the length crossed gets reported.
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At 6 layers, 45 of 253 connections stay open. The white crosses are where it
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got stuck, mostly at the two chips.
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That difficulty is how the layer count gets proposed.
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2 layers cross 454 mm of seen copper. 4 layers, 384.
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6 layers, just 11. 8, about 8. Past 6, more layers stop helping. So the
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proposal is 6.
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Confidence isn't self graded. Auditors who did none of the work judge random
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crops, and some of the claims are planted false.
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Pass one of those, and the whole sample gets thrown out. That actually
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happened here, on blocks.
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Identity clears 90. Vias, blocks and placement land around 60. Values are at
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34, because most small parts carry no marking.
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Copper scores 9, because through smooth green mask, an auditor mostly can't
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tell copper from bare board. Layers stop at 30 without outside evidence. And
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connectivity is 0, because KiCad finds more missing than expected.
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Overall is the lowest category, so the loop reports stalled, at 0. It did not
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reach 90. From photos alone, it can't: values, layers and nets need
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measurements on the real board.
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Whatever is still unknown gets a test. 119 of them, each saying what to
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measure, what result to expect, and what to change if it's different.
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We did find the real design. It went in a sealed folder as an answer key. The
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flow never reads it, the agents never see it, and only totals come out.
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Real vias went from 42% to over 95%. Vias found, from 26% to 75%.
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Copper match went from 61% to 67% on top, and from 80% to 89% on the bottom.
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And 6 layers is correct.
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Pin nets barely moved. 46% to 48%. That's the weakest result here.
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So this isn't a finished board. 45 connections stay open, and KiCad counts 441
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missing.
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Finer copper also made routing harder. New design rule errors at 6 layers went
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from 6 to 594. And these thresholds came from this one board, so a second
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board has to come next.
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Every stage stays in the flow window, so you can step back through the whole
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run and open any board along the way.
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From the first prompt to this point took about 13 hours of AI time in the main
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thread, with idle gaps cut out, plus 46 sub-agents.
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About 3.4 million output tokens and 634 million cache reads, across 1,811
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model calls. Next up: real measurements on this board, and a second board.