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AI Flow: Reverse Engineering
Public Made by Adomby adom
Photos of a PCB to a tagged KiCad copy: parts placed, copper and nets with their evidence, a schematic, a measured confidence score, bench tests and a video of the run.
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Caleb
Version 0.3.0: new copper reader, dome via filter, every layer read from the photos, net evidence, measured confidence;…
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{
"nets": [
{
"copperEvidence": {
"groupsOfSeenPins": 5,
"pinClashes": 0,
"pins": 35,
"pinsSeen": 6
},
"copperGroups": [
[
"C25.1"
],
[
"D4.2"
],
[
"TP4.1"
],
[
"C6.1",
"C7.1"
],
[
"PHOTO1.M2"
]
],
"inferredPins": [
"TP4.1",
"J1.1",
"C1.1",
"C2.1",
"C3.1",
"C4.1",
"C5.1",
"C6.1",
"C7.1",
"C8.1",
"C9.1",
"C10.1",
"C11.1",
"C12.1",
"C13.1",
"C14.1",
"C15.1",
"C16.1",
"C17.1",
"C18.1",
"C19.1",
"C20.1",
"C21.1",
"C22.1",
"C23.1",
"Q5.5",
"Q3.5",
"Q1.5",
"C24.1",
"C25.1",
"C26.1",
"U2.4",
"U2.5",
"C42.2",
"C41.1",
"R4.1",
"D4.2",
"H6.1",
"PHOTO1.M2"
],
"name": "VIN",
"nameSource": "silkscreen",
"pins": [
"C1.1",
"C10.1",
"C11.1",
"C12.1",
"C13.1",
"C14.1",
"C15.1",
"C16.1",
"C17.1",
"C18.1",
"C2.1",
"C20.1",
"C21.1",
"C22.1",
"C23.1",
"C24.1",
"C25.1",
"C26.1",
"C3.1",
"C4.1",
"C41.1",
"C42.2",
"C5.1",
"C6.1",
"C7.1",
"C8.1",
"C9.1",
"D4.2",
"H6.1",
"J1.1",
"PHOTO1.M2",
"R4.1",
"TP4.1",
"U2.4",
"U2.5"
],
"seenPins": [
"H6.1",
"H6.1",
"PHOTO1.M2"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X1",
"T-bridge-X2",
"T-bridge-X3",
"T-bridge-caps",
"T-drv-caps",
"T-logic",
"T-power-entry",
"T-vsense"
],
"why": "VIN lug (silkscreen) and XT30 pin 1 (polarity inferred: pin 1 of the library footprint)"
},
{
"copperEvidence": {
"groupsOfSeenPins": 8,
"pinClashes": 0,
"pins": 108,
"pinsSeen": 21
},
"copperGroups": [
[
"C1.2"
],
[
"C28.2"
],
[
"C29.2"
],
[
"D2.2",
"R2.2"
],
[
"U1.49"
],
[
"J11.3"
],
[
"J7.3"
],
[
"D1.2",
"D3.2",
"J10.3",
"J2.3",
"J3.3",
"J6.MP",
"PHOTO1.M22",
"Q5.5",
"R1.2",
"R25.1",
"TP5.1",
"U2.41",
"U5.5"
]
],
"inferredPins": [
"TP5.1",
"J1.2",
"C1.2",
"C2.2",
"C3.2",
"C4.2",
"C5.2",
"C6.2",
"C7.2",
"C8.2",
"C9.2",
"C10.2",
"C11.2",
"C12.2",
"C13.2",
"C14.2",
"C15.2",
"C16.2",
"C17.2",
"C18.2",
"C19.2",
"C20.2",
"C21.2",
"C22.2",
"C23.2",
"R3.2",
"D3.2",
"U2.10",
"R2.2",
"D2.2",
"U2.11",
"R1.2",
"D1.2",
"U2.20",
"C24.2",
"C25.2",
"C26.2",
"U2.32",
"U2.40",
"U2.41",
"C38.2",
"C39.2",
"C41.2",
"C40.2",
"C43.2",
"C44.2",
"U1.49",
"C53.2",
"C45.2",
"C46.2",
"C47.2",
"C48.2",
"C49.2",
"C50.2",
"SW1.2",
"C51.2",
"J10.3",
"J11.3",
"R5.2",
"C28.2",
"C27.2",
"C34.2",
"U5.5",
"U5.6",
"R13.2",
"C33.2",
"C35.2",
"C31.2",
"R10.2",
"C32.2",
"C29.2",
"R7.2",
"C30.2",
"U6.2",
"U6.8",
"C36.2",
"J2.3",
"J3.3",
"J4.3",
"J4.6",
"J5.7",
"J6.7",
"C52.2",
"J7.3",
"J8.4",
"J9.4",
"C56.2",
"R30.2",
"C55.2",
"C54.2",
"J7.8",
"JP1.2",
"U1.39",
"U1.40",
"R19.1",
"R19.2",
"H7.1",
"J6.MP",
"H4.1",
"PHOTO1.M3",
"PHOTO1.M4",
"PHOTO1.M5",
"PHOTO1.M15",
"PHOTO1.M16",
"PHOTO1.M17",
"PHOTO1.M21",
"PHOTO1.M22"
],
"name": "GND",
"nameSource": "silkscreen",
"pins": [
"C1.2",
"C10.2",
"C11.2",
"C12.2",
"C13.2",
"C14.2",
"C15.2",
"C16.2",
"C17.2",
"C18.2",
"C19.2",
"C2.2",
"C20.2",
"C21.2",
"C22.2",
"C23.2",
"C24.2",
"C25.2",
"C27.2",
"C28.2",
"C29.2",
"C3.2",
"C30.2",
"C31.2",
"C32.2",
"C33.2",
"C34.2",
"C35.2",
"C36.2",
"C38.2",
"C39.2",
"C4.2",
"C40.2",
"C41.2",
"C43.2",
"C44.2",
"C45.2",
"C46.2",
"C47.2",
"C48.2",
"C49.2",
"C5.2",
"C50.2",
"C51.2",
"C52.2",
"C53.2",
"C54.2",
"C55.2",
"C56.2",
"C6.2",
"C7.2",
"C8.2",
"C9.2",
"D1.2",
"D2.2",
"D3.2",
"H4.1",
"H7.1",
"J1.2",
"J10.3",
"J11.3",
"J2.3",
"J3.3",
"J4.3",
"J4.6",
"J5.7",
"J6.7",
"J6.MP",
"J7.3",
"J7.8",
"J8.4",
"J9.4",
"JP1.2",
"PHOTO1.M15",
"PHOTO1.M16",
"PHOTO1.M17",
"PHOTO1.M21",
"PHOTO1.M22",
"PHOTO1.M3",
"PHOTO1.M4",
"PHOTO1.M5",
"Q5.5",
"R1.2",
"R10.2",
"R13.2",
"R19.1",
"R19.2",
"R2.2",
"R25.1",
"R3.2",
"R30.2",
"R5.2",
"R7.2",
"SW1.2",
"TP5.1",
"U1.39",
"U1.40",
"U1.49",
"U2.10",
"U2.11",
"U2.20",
"U2.32",
"U2.40",
"U2.41",
"U5.5",
"U5.6",
"U6.2",
"U6.8"
],
"seenPins": [
"J7.8",
"JP1.2",
"U1.39",
"U1.40",
"R19.1",
"R19.2",
"H7.1",
"H7.1",
"J6.MP",
"H4.1",
"PHOTO1.M3",
"PHOTO1.M4",
"PHOTO1.M5",
"PHOTO1.M15",
"PHOTO1.M16",
"PHOTO1.M17",
"PHOTO1.M21",
"PHOTO1.M22"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X1",
"T-bridge-X2",
"T-bridge-X3",
"T-bridge-caps",
"T-can",
"T-mcu-supply",
"T-power-entry"
],
"why": "GND lug (silkscreen) and XT30 pin 2"
},
{
"copperEvidence": {
"groupsOfSeenPins": 3,
"pinClashes": 0,
"pins": 11,
"pinsSeen": 8
},
"copperGroups": [
[
"D3.1"
],
[
"U2.7"
],
[
"C26.2",
"H2.1",
"Q5.2",
"Q5.3",
"Q6.5",
"TP3.1"
]
],
"inferredPins": [
"TP3.1",
"Q5.1",
"Q5.2",
"Q5.3",
"Q6.5",
"D3.1",
"U2.7",
"H2.1",
"PHOTO1.M0",
"PHOTO1.M18"
],
"name": "PHASE_X1",
"nameSource": "datasheet",
"pins": [
"C26.2",
"D3.1",
"H2.1",
"PHOTO1.M0",
"PHOTO1.M18",
"Q5.1",
"Q5.2",
"Q5.3",
"Q6.5",
"TP3.1",
"U2.7"
],
"seenPins": [
"H2.1",
"H2.1",
"PHOTO1.M0",
"PHOTO1.M18"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X1"
],
"why": "half-bridge X1: high-side source and low-side drain to the X1 lug; DRV8323S SHA"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"Q5.4",
"U2.6"
],
"name": "GHA",
"nameSource": "datasheet",
"pins": [
"Q5.4",
"U2.6"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X1"
],
"why": "DRV8323S GHA to the high-side gate"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"Q6.4",
"U2.8"
],
"name": "GLA",
"nameSource": "datasheet",
"pins": [
"Q6.4",
"U2.8"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X1"
],
"why": "DRV8323S GLA to the low-side gate"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 5,
"pinsSeen": 3
},
"copperGroups": [
[
"Q6.1",
"Q6.2",
"Q6.3"
]
],
"inferredPins": [
"Q6.1",
"Q6.2",
"Q6.3",
"R3.1",
"U2.9"
],
"name": "SPA",
"nameSource": "datasheet",
"pins": [
"Q6.1",
"Q6.2",
"Q6.3",
"R3.1",
"U2.9"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X1"
],
"why": "low-side source to the shunt high side and DRV8323S SPA"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 9,
"pinsSeen": 5
},
"copperGroups": [
[
"Q3.1",
"Q3.2",
"Q3.5",
"Q4.5",
"TP2.1"
]
],
"inferredPins": [
"TP2.1",
"Q3.1",
"Q3.2",
"Q3.3",
"Q4.5",
"D2.1",
"U2.14",
"H3.1"
],
"name": "PHASE_X2",
"nameSource": "datasheet",
"pins": [
"D2.1",
"H3.1",
"Q3.1",
"Q3.2",
"Q3.3",
"Q3.5",
"Q4.5",
"TP2.1",
"U2.14"
],
"seenPins": [
"H3.1",
"H3.1"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X2"
],
"why": "half-bridge X2: high-side source and low-side drain to the X2 lug; DRV8323S SHB"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"Q3.4",
"U2.15"
],
"name": "GHB",
"nameSource": "datasheet",
"pins": [
"Q3.4",
"U2.15"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X2"
],
"why": "DRV8323S GHB to the high-side gate"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"Q4.4",
"U2.13"
],
"name": "GLB",
"nameSource": "datasheet",
"pins": [
"Q4.4",
"U2.13"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X2"
],
"why": "DRV8323S GLB to the low-side gate"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 5,
"pinsSeen": 3
},
"copperGroups": [
[
"Q4.1",
"Q4.2",
"Q4.3"
]
],
"inferredPins": [
"Q4.1",
"Q4.2",
"Q4.3",
"R2.1",
"U2.12"
],
"name": "SPB",
"nameSource": "datasheet",
"pins": [
"Q4.1",
"Q4.2",
"Q4.3",
"R2.1",
"U2.12"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X2"
],
"why": "low-side source to the shunt high side and DRV8323S SPB"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 11,
"pinsSeen": 6
},
"copperGroups": [
[
"H1.1",
"PHOTO1.M19",
"Q1.2",
"Q1.5",
"Q2.5",
"TP1.1"
]
],
"inferredPins": [
"TP1.1",
"Q1.1",
"Q1.2",
"Q1.3",
"Q2.5",
"D1.1",
"U2.17",
"H1.1",
"PHOTO1.M1",
"PHOTO1.M19"
],
"name": "PHASE_X3",
"nameSource": "datasheet",
"pins": [
"D1.1",
"H1.1",
"PHOTO1.M1",
"PHOTO1.M19",
"Q1.1",
"Q1.2",
"Q1.3",
"Q1.5",
"Q2.5",
"TP1.1",
"U2.17"
],
"seenPins": [
"H1.1",
"H1.1",
"PHOTO1.M1",
"PHOTO1.M19"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X3"
],
"why": "half-bridge X3: high-side source and low-side drain to the X3 lug; DRV8323S SHC"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"Q1.4",
"U2.16"
],
"name": "GHC",
"nameSource": "datasheet",
"pins": [
"Q1.4",
"U2.16"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X3"
],
"why": "DRV8323S GHC to the high-side gate"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 1
},
"copperGroups": [
[
"Q2.4"
]
],
"inferredPins": [
"Q2.4",
"U2.18"
],
"name": "GLC",
"nameSource": "datasheet",
"pins": [
"Q2.4",
"U2.18"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X3"
],
"why": "DRV8323S GLC to the low-side gate"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 5,
"pinsSeen": 1
},
"copperGroups": [
[
"Q2.1"
]
],
"inferredPins": [
"Q2.1",
"Q2.2",
"Q2.3",
"R1.1",
"U2.19"
],
"name": "SPC",
"nameSource": "datasheet",
"pins": [
"Q2.1",
"Q2.2",
"Q2.3",
"R1.1",
"U2.19"
],
"tag": "INFERRED",
"tests": [
"T-bridge-X3"
],
"why": "low-side source to the shunt high side and DRV8323S SPC"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 1,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U2.1",
"C37.1"
],
"name": "DRV_CPL",
"nameSource": "datasheet",
"pins": [
"U2.1"
],
"tag": "INFERRED",
"tests": [
"T-drv-caps"
],
"why": "charge-pump flying capacitor 47 nF between CPH and CPL (TI typical application)"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U2.2",
"C37.2"
],
"name": "DRV_CPH",
"nameSource": "circuit",
"pins": [
"C37.2",
"U2.2"
],
"tag": "INFERRED",
"tests": [
"T-drv-caps"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U2.3",
"C42.1"
],
"name": "DRV_VCP",
"nameSource": "circuit",
"pins": [
"C42.1",
"U2.3"
],
"tag": "INFERRED",
"tests": [
"T-drv-caps"
],
"why": "VCP to VM 1 uF"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U2.33",
"C38.1"
],
"name": "DRV_DVDD",
"nameSource": "circuit",
"pins": [
"C38.1",
"U2.33"
],
"tag": "INFERRED",
"tests": [
"T-drv-caps"
],
"why": "DVDD 1 uF to GND"
},
{
"copperEvidence": {
"groupsOfSeenPins": 2,
"pinClashes": 0,
"pins": 31,
"pinsSeen": 2
},
"copperGroups": [
[
"U1.23"
],
[
"U4.2"
]
],
"inferredPins": [
"U2.24",
"C39.1",
"U1.1",
"U1.20",
"U1.23",
"U1.35",
"U1.48",
"R28.1",
"C45.1",
"C46.1",
"C47.1",
"C48.1",
"C49.1",
"C50.1",
"R17.2",
"R18.2",
"J10.1",
"J11.1",
"LED1.2",
"LED2.2",
"U4.2",
"R6.1",
"C30.1",
"U6.5",
"J5.2",
"J6.2",
"J7.2",
"R22.2",
"R23.2",
"J12.1",
"J13.1"
],
"name": "+3V3",
"nameSource": "circuit",
"pins": [
"C30.1",
"C39.1",
"C45.1",
"C46.1",
"C47.1",
"C48.1",
"C49.1",
"C50.1",
"J10.1",
"J11.1",
"J12.1",
"J13.1",
"J5.2",
"J6.2",
"J7.2",
"LED1.2",
"LED2.2",
"R17.2",
"R18.2",
"R22.2",
"R23.2",
"R28.1",
"R6.1",
"U1.1",
"U1.20",
"U1.23",
"U1.35",
"U1.48",
"U2.24",
"U4.2",
"U6.5"
],
"tag": "INFERRED",
"tests": [
"T-aux",
"T-can",
"T-drv-caps",
"T-headers",
"T-leds",
"T-logic",
"T-mcu-supply"
],
"why": "VREF from the 3.3 V rail, 0.1 uF"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 1
},
"copperGroups": [
[
"R14.1"
]
],
"inferredPins": [
"U2.23",
"R14.1"
],
"name": "SOA",
"nameSource": "datasheet",
"pins": [
"R14.1",
"U2.23"
],
"tag": "INFERRED",
"tests": [
"T-drv-csa"
],
"why": "DRV8323S SOA through 22 Ω"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"R14.2",
"C40.1",
"U1.8"
],
"name": "SOA_ADC",
"nameSource": "circuit",
"pins": [
"C40.1",
"R14.2",
"U1.8"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "filtered current-sense output to the MCU ADC"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U2.22",
"R15.1"
],
"name": "SOB",
"nameSource": "datasheet",
"pins": [
"R15.1",
"U2.22"
],
"tag": "INFERRED",
"tests": [
"T-drv-csa"
],
"why": "DRV8323S SOB through 22 Ω"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 1
},
"copperGroups": [
[
"U1.9"
]
],
"inferredPins": [
"R15.2",
"C43.1",
"U1.9"
],
"name": "SOB_ADC",
"nameSource": "circuit",
"pins": [
"C43.1",
"R15.2",
"U1.9"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "filtered current-sense output to the MCU ADC"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 1
},
"copperGroups": [
[
"U2.21"
]
],
"inferredPins": [
"U2.21",
"R16.1"
],
"name": "SOC",
"nameSource": "datasheet",
"pins": [
"R16.1",
"U2.21"
],
"tag": "INFERRED",
"tests": [
"T-drv-csa"
],
"why": "DRV8323S SOC through 22 Ω"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"R16.2",
"C44.1",
"U1.10"
],
"name": "SOC_ADC",
"nameSource": "circuit",
"pins": [
"C44.1",
"R16.2",
"U1.10"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "filtered current-sense output to the MCU ADC"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 1
},
"copperGroups": [
[
"U1.21"
]
],
"inferredPins": [
"U1.21",
"R28.2",
"C53.1"
],
"name": "+3V3A",
"nameSource": "circuit",
"pins": [
"C53.1",
"R28.2",
"U1.21"
],
"tag": "INFERRED",
"tests": [
"T-mcu-supply"
],
"why": "VDDA through a 10 Ω filter (the 10 Ω resistor and capacitor by the MCU)"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 4,
"pinsSeen": 1
},
"copperGroups": [
[
"U1.7"
]
],
"inferredPins": [
"U1.7",
"SW1.1",
"C51.1",
"U1.6"
],
"name": "NRST",
"nameSource": "circuit",
"pins": [
"C51.1",
"SW1.1",
"U1.6",
"U1.7"
],
"seenPins": [
"U1.6"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "PG10 is NRST; the reset button and its capacitor"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.30",
"U2.34"
],
"name": "INHA",
"nameSource": "circuit",
"pins": [
"U1.30",
"U2.34"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.31",
"U2.36"
],
"name": "INHB",
"nameSource": "circuit",
"pins": [
"U1.31",
"U2.36"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.32",
"U2.38"
],
"name": "INHC",
"nameSource": "circuit",
"pins": [
"U1.32",
"U2.38"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.26",
"U2.35"
],
"name": "INLA",
"nameSource": "circuit",
"pins": [
"U1.26",
"U2.35"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.27",
"U2.37"
],
"name": "INLB",
"nameSource": "circuit",
"pins": [
"U1.27",
"U2.37"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 1
},
"copperGroups": [
[
"U1.28"
]
],
"inferredPins": [
"U1.28",
"U2.39"
],
"name": "INLC",
"nameSource": "circuit",
"pins": [
"U1.28",
"U2.39"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.13",
"U2.28"
],
"name": "DRV_SCLK",
"nameSource": "circuit",
"pins": [
"U1.13",
"U2.28"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.14",
"U2.26",
"R18.1"
],
"name": "DRV_SDO",
"nameSource": "circuit",
"pins": [
"R18.1",
"U1.14",
"U2.26"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.15",
"U2.27"
],
"name": "DRV_SDI",
"nameSource": "circuit",
"pins": [
"U1.15",
"U2.27"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.12",
"U2.29"
],
"name": "DRV_nSCS",
"nameSource": "circuit",
"pins": [
"U1.12",
"U2.29"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 1
},
"copperGroups": [
[
"U2.30"
]
],
"inferredPins": [
"U1.44",
"U2.30"
],
"name": "DRV_EN",
"nameSource": "circuit",
"pins": [
"U1.44",
"U2.30"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.45",
"U2.31"
],
"name": "DRV_CAL",
"nameSource": "circuit",
"pins": [
"U1.45",
"U2.31"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 5,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.19",
"U2.25",
"R17.1",
"U1.5",
"U1.18"
],
"name": "DRV_nFAULT",
"nameSource": "circuit",
"pins": [
"R17.1",
"U1.18",
"U1.19",
"U1.5",
"U2.25"
],
"seenPins": [
"U1.5",
"U1.18"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.33",
"U6.4"
],
"name": "CAN_RX",
"nameSource": "circuit",
"pins": [
"U1.33",
"U6.4"
],
"tag": "INFERRED",
"tests": [
"T-can",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.34",
"U6.1"
],
"name": "CAN_TX",
"nameSource": "circuit",
"pins": [
"U1.34",
"U6.1"
],
"tag": "INFERRED",
"tests": [
"T-can",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.36",
"J10.4",
"J11.4"
],
"name": "SWDIO",
"nameSource": "circuit",
"pins": [
"J10.4",
"J11.4",
"U1.36"
],
"tag": "INFERRED",
"tests": [
"T-headers",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.37",
"J10.2",
"J11.2"
],
"name": "SWCLK",
"nameSource": "circuit",
"pins": [
"J10.2",
"J11.2",
"U1.37"
],
"tag": "INFERRED",
"tests": [
"T-headers",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 4,
"pinsSeen": 1
},
"copperGroups": [
[
"R4.2"
]
],
"inferredPins": [
"U1.11",
"R4.2",
"R5.1",
"C28.1"
],
"name": "VSENSE",
"nameSource": "circuit",
"pins": [
"C28.1",
"R4.2",
"R5.1",
"U1.11"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap",
"T-vsense"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.17",
"R29.2",
"C54.1"
],
"name": "NTC_ADC",
"nameSource": "circuit",
"pins": [
"C54.1",
"R29.2",
"U1.17"
],
"tag": "INFERRED",
"tests": [
"T-mcu-pinmap",
"T-ntc"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.46",
"R31.1"
],
"name": "FAN_PWM_MCU",
"nameSource": "circuit",
"pins": [
"R31.1",
"U1.46"
],
"tag": "INFERRED",
"tests": [
"T-fan",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.47",
"R32.1"
],
"name": "FAN_TACH",
"nameSource": "circuit",
"pins": [
"R32.1",
"U1.47"
],
"tag": "INFERRED",
"tests": [
"T-fan",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.2",
"R20.2"
],
"name": "LED1_K",
"nameSource": "circuit",
"pins": [
"R20.2",
"U1.2"
],
"tag": "INFERRED",
"tests": [
"T-leds",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 1
},
"copperGroups": [
[
"U1.4"
]
],
"inferredPins": [
"U1.3",
"R21.2",
"U1.4"
],
"name": "LED2_K",
"nameSource": "circuit",
"pins": [
"R21.2",
"U1.3",
"U1.4"
],
"seenPins": [
"U1.4"
],
"tag": "INFERRED",
"tests": [
"T-leds",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.22",
"R24.1"
],
"name": "AUX_A_MCU",
"nameSource": "circuit",
"pins": [
"R24.1",
"U1.22"
],
"tag": "INFERRED",
"tests": [
"T-aux",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 1,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.24",
"R25.1"
],
"name": "AUX_B_MCU",
"nameSource": "circuit",
"pins": [
"U1.24"
],
"tag": "INFERRED",
"tests": [
"T-aux",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 1
},
"copperGroups": [
[
"U1.25"
]
],
"inferredPins": [
"U1.25",
"R26.1"
],
"name": "AUX_C_MCU",
"nameSource": "circuit",
"pins": [
"R26.1",
"U1.25"
],
"tag": "INFERRED",
"tests": [
"T-aux",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 1
},
"copperGroups": [
[
"U1.29"
]
],
"inferredPins": [
"U1.29",
"R27.1"
],
"name": "AUX_D_MCU",
"nameSource": "circuit",
"pins": [
"R27.1",
"U1.29"
],
"tag": "INFERRED",
"tests": [
"T-aux",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.41",
"J7.4"
],
"name": "EXP_SCLK",
"nameSource": "circuit",
"pins": [
"J7.4",
"U1.41"
],
"tag": "INFERRED",
"tests": [
"T-headers",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.42",
"J7.5",
"R22.1"
],
"name": "EXP_MISO_SDA",
"nameSource": "circuit",
"pins": [
"J7.5",
"R22.1",
"U1.42"
],
"tag": "INFERRED",
"tests": [
"T-headers",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.43",
"J7.6",
"R23.1"
],
"name": "EXP_MOSI_SCL",
"nameSource": "circuit",
"pins": [
"J7.6",
"R23.1",
"U1.43"
],
"tag": "INFERRED",
"tests": [
"T-headers",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U1.38",
"J7.7"
],
"name": "EXP_GPIO",
"nameSource": "circuit",
"pins": [
"J7.7",
"U1.38"
],
"tag": "INFERRED",
"tests": [
"T-headers",
"T-mcu-pinmap"
],
"why": "MCU pin chosen to carry the needed peripheral (TIM1 CH1-3 and CH1N-3N for the six PWM, SPI1 to the driver, FDCAN1 on PA11/PA12, SWD on PA13/PA14, ADC for sensing); the original pin map is under the mask and not seen"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"LED1.1",
"R20.1"
],
"name": "LED1_A",
"nameSource": "circuit",
"pins": [
"LED1.1",
"R20.1"
],
"tag": "INFERRED",
"tests": [
"T-leds"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 2,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"LED2.1",
"R21.1"
],
"name": "LED2_A",
"nameSource": "circuit",
"pins": [
"LED2.1",
"R21.1"
],
"tag": "INFERRED",
"tests": [
"T-leds"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 7,
"pinsSeen": 3
},
"copperGroups": [
[
"C19.1",
"C37.1",
"D4.1"
]
],
"inferredPins": [
"D4.1",
"C27.1",
"C34.1",
"U5.2",
"U5.3"
],
"name": "VIN_LOGIC",
"nameSource": "circuit",
"pins": [
"C19.1",
"C27.1",
"C34.1",
"C37.1",
"D4.1",
"U5.2",
"U5.3"
],
"tag": "INFERRED",
"tests": [
"T-logic"
],
"why": "Schottky D4 from VIN feeds the regulators"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 1,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U5.1"
],
"name": "BUCK_BST",
"nameSource": "circuit",
"pins": [
"U5.1"
],
"tag": "INFERRED",
"tests": [
"T-logic"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U5.4",
"R12.2",
"R13.1"
],
"name": "BUCK_FB",
"nameSource": "circuit",
"pins": [
"R12.2",
"R13.1",
"U5.4"
],
"tag": "INFERRED",
"tests": [
"T-logic"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U5.7",
"U5.8",
"L1.1"
],
"name": "BUCK_SW",
"nameSource": "circuit",
"pins": [
"L1.1",
"U5.7",
"U5.8"
],
"tag": "INFERRED",
"tests": [
"T-logic"
],
"why": "buck pin functions are placeholders: the IC marking is unreadable"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 9,
"pinsSeen": 1
},
"copperGroups": [
[
"C31.1"
]
],
"inferredPins": [
"L1.2",
"R12.1",
"C33.1",
"C35.1",
"U3.3",
"C31.1",
"J8.3",
"J9.3",
"C56.1"
],
"name": "+12V",
"nameSource": "circuit",
"pins": [
"C31.1",
"C33.1",
"C35.1",
"C56.1",
"J8.3",
"J9.3",
"L1.2",
"R12.1",
"U3.3"
],
"tag": "INFERRED",
"tests": [
"T-headers",
"T-logic"
],
"why": "buck output, 40.2 kΩ upper feedback (59C)"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 12,
"pinsSeen": 1
},
"copperGroups": [
[
"U3.2"
]
],
"inferredPins": [
"U3.2",
"R8.1",
"C32.1",
"U4.3",
"C29.1",
"U6.3",
"C36.1",
"J5.1",
"J6.1",
"C52.1",
"J7.1",
"R11.1"
],
"name": "+5V",
"nameSource": "circuit",
"pins": [
"C29.1",
"C32.1",
"C36.1",
"C52.1",
"J5.1",
"J6.1",
"J7.1",
"R11.1",
"R8.1",
"U3.2",
"U4.3",
"U6.3"
],
"seenPins": [
"R11.1"
],
"tag": "INFERRED",
"tests": [
"T-can",
"T-headers",
"T-logic"
],
"why": "left SOT-223 output; divider 240/620 gives 1.25 V x (1 + 620/240) = 4.48 V"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 4,
"pinsSeen": 1
},
"copperGroups": [
[
"U3.1"
]
],
"inferredPins": [
"U3.1",
"R8.2",
"R10.1",
"R9.2"
],
"name": "LDO5_ADJ",
"nameSource": "circuit",
"pins": [
"R10.1",
"R8.2",
"R9.2",
"U3.1"
],
"seenPins": [
"R9.2"
],
"tag": "INFERRED",
"tests": [
"T-logic"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"U4.1",
"R6.2",
"R7.1"
],
"name": "LDO3_ADJ",
"nameSource": "circuit",
"pins": [
"R6.2",
"R7.1",
"U4.1"
],
"tag": "INFERRED",
"tests": [
"T-logic"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 5,
"pinsSeen": 1
},
"copperGroups": [
[
"J4.2"
]
],
"inferredPins": [
"U6.6",
"J2.2",
"J3.2",
"J4.2",
"J4.4"
],
"name": "CAN_L",
"nameSource": "silkscreen",
"pins": [
"J2.2",
"J3.2",
"J4.2",
"J4.4",
"U6.6"
],
"tag": "INFERRED",
"tests": [
"T-can"
],
"why": "transceiver CANL to both ports (terminal blocks and the 2.0 mm header: silkscreen + − ⏚ − + ⏚)"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 7,
"pinsSeen": 1
},
"copperGroups": [
[
"JP1.1"
]
],
"inferredPins": [
"U6.7",
"J2.1",
"J3.1",
"J4.1",
"J4.5",
"JP1.1",
"R9.1"
],
"name": "CAN_H",
"nameSource": "circuit",
"pins": [
"J2.1",
"J3.1",
"J4.1",
"J4.5",
"JP1.1",
"R9.1",
"U6.7"
],
"seenPins": [
"R9.1"
],
"tag": "INFERRED",
"tests": [
"T-can"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 1
},
"copperGroups": [
[
"R24.2"
]
],
"inferredPins": [
"J5.3",
"J6.3",
"R24.2"
],
"name": "AUX_A",
"nameSource": "circuit",
"pins": [
"J5.3",
"J6.3",
"R24.2"
],
"tag": "INFERRED",
"tests": [
"T-aux",
"T-headers"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"J5.4",
"J6.4",
"R25.2"
],
"name": "AUX_B",
"nameSource": "circuit",
"pins": [
"J5.4",
"J6.4",
"R25.2"
],
"tag": "INFERRED",
"tests": [
"T-aux",
"T-headers"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"J5.5",
"J6.5",
"R26.2"
],
"name": "AUX_C",
"nameSource": "circuit",
"pins": [
"J5.5",
"J6.5",
"R26.2"
],
"tag": "INFERRED",
"tests": [
"T-aux",
"T-headers"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"J5.6",
"J6.6",
"R27.2"
],
"name": "AUX_D",
"nameSource": "circuit",
"pins": [
"J5.6",
"J6.6",
"R27.2"
],
"tag": "INFERRED",
"tests": [
"T-aux",
"T-headers"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 0,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 0
},
"copperGroups": [],
"inferredPins": [
"J8.1",
"J9.1",
"R31.2"
],
"name": "FAN_PWM",
"nameSource": "circuit",
"pins": [
"J8.1",
"J9.1",
"R31.2"
],
"tag": "INFERRED",
"tests": [
"T-fan",
"T-headers"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 1,
"pinClashes": 0,
"pins": 3,
"pinsSeen": 1
},
"copperGroups": [
[
"J9.2"
]
],
"inferredPins": [
"J8.2",
"J9.2",
"R32.2"
],
"name": "FAN_SENSE",
"nameSource": "circuit",
"pins": [
"J8.2",
"J9.2",
"R32.2"
],
"tag": "INFERRED",
"tests": [
"T-fan",
"T-headers"
],
"why": "connection chosen to fit the circuit"
},
{
"copperEvidence": {
"groupsOfSeenPins": 2,
"pinClashes": 0,
"pins": 5,
"pinsSeen": 2
},
"copperGroups": [
[
"R29.1"
],
[
"J12.2"
]
],
"inferredPins": [
"J12.2",
"J13.2",
"R30.1",
"C55.1",
"R29.1"
],
"name": "NTC",
"nameSource": "circuit",
"pins": [
"C55.1",
"J12.2",
"J13.2",
"R29.1",
"R30.1"
],
"tag": "INFERRED",
"tests": [
"T-headers",
"T-ntc"
],
"why": "connection chosen to fit the circuit"
}
]
}