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AI Flow: Reverse Engineering
Public Made by Adomby adom
Photos of a PCB to a tagged KiCad copy: parts placed, copper and nets with their evidence, a schematic, a measured confidence score, bench tests and a video of the run.
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Caleb
Version 0.3.0: new copper reader, dome via filter, every layer read from the photos, net evidence, measured confidence;…
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{
"candidates": [
{
"connections": 267,
"drcErrors": 718,
"drcTypes": {
"clearance": 394,
"copper_edge_clearance": 2,
"hole_clearance": 161,
"shorting_items": 91,
"solder_mask_bridge": 70
},
"inheritedErrors": 432,
"kicadOpen": 358,
"layerUse": [
{
"layer": "F.Cu",
"plane": null,
"trackMm": 822.9
},
{
"layer": "B.Cu",
"plane": null,
"trackMm": 852.7
}
],
"layers": 2,
"log": "reverse-flow/routes/L2/route.log",
"narrowedPower": [
"VIN",
"GND",
"VIN_LOGIC",
"PHASE_X3",
"PHASE_X2",
"PHASE_X1",
"+3V3",
"+12V",
"DRV_DVDD"
],
"open": 47,
"passes": 3,
"planes": [],
"ripups": 585,
"rules": "kicad-default",
"run": "reverse-flow/routes/L2",
"seconds": 200.4,
"seenCrossingMm": 453.9,
"seenTracksDisplaced": 1208,
"stop": "time limit of 200 s",
"trackMm": 1675.6,
"vias": 239
},
{
"connections": 253,
"drcErrors": 475,
"drcTypes": {
"clearance": 319,
"copper_edge_clearance": 2,
"hole_clearance": 139,
"shorting_items": 9,
"solder_mask_bridge": 6
},
"inheritedErrors": 426,
"kicadOpen": 340,
"layerUse": [
{
"layer": "F.Cu",
"plane": null,
"trackMm": 790.6
},
{
"layer": "In1.Cu",
"plane": "GND",
"trackMm": 0.0
},
{
"layer": "In2.Cu",
"plane": "+3V3",
"trackMm": 0.0
},
{
"layer": "B.Cu",
"plane": null,
"trackMm": 802.5
}
],
"layers": 4,
"log": "reverse-flow/routes/L4/route.log",
"narrowedPower": [
"VIN",
"PHASE_X3",
"PHASE_X2",
"PHASE_X1",
"+12V",
"DRV_DVDD"
],
"open": 43,
"passes": 4,
"planes": [
{
"layer": "In1.Cu",
"net": "GND",
"tag": "INFERRED",
"tests": [
"T-layers"
],
"why": "chosen for this stackup: the largest power nets on the layers next to the outer faces"
},
{
"layer": "In2.Cu",
"net": "+3V3",
"tag": "INFERRED",
"tests": [
"T-layers"
],
"why": "chosen for this stackup: the largest power nets on the layers next to the outer faces"
}
],
"ripups": 587,
"rules": "kicad-default",
"run": "reverse-flow/routes/L4",
"seconds": 176.3,
"seenCrossingMm": 384.1,
"seenTracksDisplaced": 1112,
"stop": "3 passes closed nothing new: this stackup is the limit",
"trackMm": 1593.1,
"vias": 229
},
{
"connections": 253,
"drcErrors": 594,
"drcTypes": {
"clearance": 325,
"hole_clearance": 154,
"shorting_items": 78,
"solder_mask_bridge": 37
},
"inheritedErrors": 426,
"kicadOpen": 441,
"layerUse": [
{
"layer": "F.Cu",
"plane": null,
"trackMm": 134.7
},
{
"layer": "In1.Cu",
"plane": "GND",
"trackMm": 0.0
},
{
"layer": "In2.Cu",
"plane": null,
"trackMm": 493.3
},
{
"layer": "In3.Cu",
"plane": null,
"trackMm": 321.8
},
{
"layer": "In4.Cu",
"plane": "+3V3",
"trackMm": 0.0
},
{
"layer": "B.Cu",
"plane": null,
"trackMm": 38.9
}
],
"layers": 6,
"log": "reverse-flow/routes/L6/route.log",
"narrowedPower": [
"VIN",
"VIN_LOGIC",
"PHASE_X3",
"PHASE_X2",
"PHASE_X1",
"+12V",
"DRV_DVDD"
],
"open": 45,
"passes": 4,
"planes": [
{
"layer": "In1.Cu",
"net": "GND",
"tag": "INFERRED",
"tests": [
"T-layers"
],
"why": "chosen for this stackup: the largest power nets on the layers next to the outer faces"
},
{
"layer": "In4.Cu",
"net": "+3V3",
"tag": "INFERRED",
"tests": [
"T-layers"
],
"why": "chosen for this stackup: the largest power nets on the layers next to the outer faces"
}
],
"ripups": 394,
"rules": "kicad-default",
"run": "reverse-flow/routes/L6",
"seconds": 154.9,
"seenCrossingMm": 11.2,
"seenTracksDisplaced": 358,
"stop": "3 passes closed nothing new: this stackup is the limit",
"trackMm": 988.7,
"vias": 150
},
{
"connections": 253,
"drcErrors": 602,
"drcTypes": {
"clearance": 357,
"hole_clearance": 136,
"shorting_items": 59,
"solder_mask_bridge": 50
},
"inheritedErrors": 419,
"kicadOpen": 452,
"layerUse": [
{
"layer": "F.Cu",
"plane": null,
"trackMm": 83.4
},
{
"layer": "In1.Cu",
"plane": "GND",
"trackMm": 0.0
},
{
"layer": "In2.Cu",
"plane": null,
"trackMm": 342.9
},
{
"layer": "In3.Cu",
"plane": null,
"trackMm": 244.6
},
{
"layer": "In4.Cu",
"plane": null,
"trackMm": 165.7
},
{
"layer": "In5.Cu",
"plane": null,
"trackMm": 92.1
},
{
"layer": "In6.Cu",
"plane": "+3V3",
"trackMm": 0.0
},
{
"layer": "B.Cu",
"plane": null,
"trackMm": 16.6
}
],
"layers": 8,
"log": "reverse-flow/routes/L8/route.log",
"narrowedPower": [
"VIN",
"VIN_LOGIC",
"PHASE_X3",
"PHASE_X2",
"+5V",
"DRV_DVDD"
],
"open": 45,
"passes": 4,
"planes": [
{
"layer": "In1.Cu",
"net": "GND",
"tag": "INFERRED",
"tests": [
"T-layers"
],
"why": "chosen for this stackup: the largest power nets on the layers next to the outer faces"
},
{
"layer": "In6.Cu",
"net": "+3V3",
"tag": "INFERRED",
"tests": [
"T-layers"
],
"why": "chosen for this stackup: the largest power nets on the layers next to the outer faces"
}
],
"ripups": 328,
"rules": "kicad-default",
"run": "reverse-flow/routes/L8",
"seconds": 153.2,
"seenCrossingMm": 8.4,
"seenTracksDisplaced": 271,
"stop": "3 passes closed nothing new: this stackup is the limit",
"trackMm": 945.2,
"vias": 139
}
],
"escalation": "not closed; last: 8 layers: 45 open, 602 new DRC errors, 452 missing per KiCad (3 passes closed nothing new: this stackup is the limit)",
"openNote": "45 connection(s) stay open at 6 layers: GND (R10.2); GND (C56.2); GND (); PHASE_X3 (U2.17); GHB (U2.15); GLB (U2.13); VSENSE (U1.11); CAN_H (J3.1); CAN_L (J2.2); +3V3 (U2.24); +3V3 (U1.20); +3V3 (U1.35); +3V3 (U1.23); EXP_SCLK (U1.41); EXP_MOSI_SCL (U1.43); EXP_GPIO (U1.38); +12V (R12.1); SWCLK (U1.37); SWDIO (U1.36); BUCK_FB (U5.4); BUCK_FB (R13.1); CAN_TX (U1.34); DRV_CPH (U2.2); SOB (R15.1); SOA (U2.23); DRV_nFAULT (U2.25); DRV_nFAULT (U1.5); DRV_SDO (U2.26); DRV_SDO (U1.14); DRV_SCLK (U1.13); DRV_nSCS (U2.29); DRV_EN (U1.44); DRV_CAL (U2.31); INHA (U2.34); INLA (U2.35); INHB (U1.31); INLB (U2.37); INHC (U2.38); SOA_ADC (U1.8); SOC_ADC (U1.10); LED1_K (U1.2); NTC_ADC (U1.17); AUX_A_MCU (U1.22); FAN_PWM_MCU (U1.46); FAN_TACH (U1.47)",
"planes": [
{
"layer": "In1.Cu",
"net": "GND",
"tag": "INFERRED",
"tests": [
"T-layers"
],
"why": "chosen for this stackup: the largest power nets on the layers next to the outer faces"
},
{
"layer": "In4.Cu",
"net": "+3V3",
"tag": "INFERRED",
"tests": [
"T-layers"
],
"why": "chosen for this stackup: the largest power nets on the layers next to the outer faces"
}
],
"proposed": 6,
"rulesExperiment": {
"candidates": [
{
"layers": 4,
"open": 30,
"seenCrossingMm": 385.2,
"trackMm": 1260.2,
"vias": 282
},
{
"layers": 6,
"open": 2,
"seenCrossingMm": 39.0,
"trackMm": 1556.2,
"vias": 288
}
],
"folder": "reverse-flow/routes-experiment-jlc",
"why": "The same seen copy routed with JLC 4-layer capabilities (0.127 track and clearance, 0.45/0.2 via) to test whether the open fan-outs are a rules limit. KiCad's shared service checks only default rules, so its DRC counts on this run do not apply."
},
"tag": "INFERRED",
"tests": [
"T-layers"
],
"trail": [
"2 layers: 47 of 267 connections open, 718 new DRC errors, 239 vias, 1676 mm of track, 454 mm crossing seen copper",
"4 layers: 43 of 253 connections open, 475 new DRC errors, 229 vias, 1593 mm of track, 384 mm crossing seen copper",
"6 layers: 45 of 253 connections open, 594 new DRC errors, 150 vias, 989 mm of track, 11 mm crossing seen copper",
"8 layers: 45 of 253 connections open, 602 new DRC errors, 139 vias, 945 mm of track, 8 mm crossing seen copper"
],
"why": "no stackup closed every connection. 6 layers is the smallest beyond which more layers stop helping. 2 layers: 47 of 267 connections open, 718 new DRC errors, 239 vias, 1676 mm of track, 454 mm crossing seen copper; 4 layers: 43 of 253 connections open, 475 new DRC errors, 229 vias, 1593 mm of track, 384 mm crossing seen copper; 6 layers: 45 of 253 connections open, 594 new DRC errors, 150 vias, 989 mm of track, 11 mm crossing seen copper; 8 layers: 45 of 253 connections open, 602 new DRC errors, 139 vias, 945 mm of track, 8 mm crossing seen copper"
}