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AI Flow: Reverse Engineering
Public Made by Adomby adom
Photos of a PCB to a tagged KiCad copy: parts placed, copper and nets with their evidence, a schematic, a measured confidence score, bench tests and a video of the run.
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Caleb
Add the Driver board KiCad copy, data and pictures
5d462f7
Driver board: reverse engineered from photos
Run of adom-aiflow-reverse 0.2 on Driver1.JPG to Driver4.jpg only, updated 2026-11-04. The generated tables (evidence counts, every open item, the tests) are in report-tables.md.
Result: a 6-layer proposal, with copper traced from the photos on both faces. No stackup closes every connection at KiCad default rules, so this is not a finished board. 34 of 249 connections stay open at 6 layers, nearly all fan-outs at the two QFNs.
What the board is
A three-phase BLDC motor controller, 73.65 x 61.78 mm with 2.5 mm corners. A TI DRV8323S gate driver (marking read, confirmed against TI's product page) drives six TDSON-8 MOSFETs in three half-bridges to the X1, X2 and X3 lugs, with 2 mΩ shunts (R002) on the low sides. An STM32G4 (silkscreen; package marking unreadable) controls it. Logic power comes through a Schottky (SS210) from VIN into an 8-pin SOT-23 buck with a 100 µH inductor, then two adjustable SOT-223 regulators whose dividers give 4.48 V and 3.28 V. The board also has CAN (SOIC-8 transceiver, terminal blocks, header, termination jumper), an AUX port, an SPI or I2C expansion header, a 4-pin fan header, a motor NTC input, SWD and a reset button.
How it was measured
| Step | Result |
|---|---|
| Photos | Outline found in all four photos (connectors over the edge left out of the fit); bottom turned over top-to-bottom (38 holes agree, 2 disagree) |
| Scale | 46.599 px/mm from the 2.0 and 2.54 mm header rows. The DRV8323S body (6 x 6 mm, TI; it measures 41 px/mm) only picks the pitch standard, so the number rests on the holes alone. Bottom aligned to top on 40 holes, 0.204 mm residual |
| 1 Parts | 137 parts. 103 placed by their own pads on the photo, 12 from a body or plated-hole centre, the rest by direct reading. 673 detected candidates all accounted for |
| 2 Blocks | 11 blocks from silkscreen and topology |
| 3 Copper | 1444 islands read from the photos: 116 pours and 314 tracks on the board, 1028 vias kept of 2681 candidates, up to 338 of them likely false, on silkscreen or other pale pixels |
| 4 Copy | KiCad board with the traced pours filled as photographed. 146 DRC errors before routing: 62 courtyard overlaps, 59 clearance, 30 board edge, 3 solder mask bridge, 1 hole in a courtyard |
| 5 Connections | 77 nets, completed from TI SLVSDJ3D (DRV8323S pins), KiCad's ST-derived STM32G431 symbol and inference. 99 pins disagree with the copper they appear to touch and are reported, not applied |
| 5 Layers | 6 proposed. See below |
| 6 Review | 4 passes; the last changed nothing |
| 7 Tests | 119 tests covering the open items |
Layer count
Rules: KiCad default (0.2 mm track and clearance, 0.6/0.3 mm via, 0.5 mm edge), set at the start and used by the zones, router and DRC.
| Layers | Open of 249 | New DRC errors | Missing per KiCad | Crossing seen copper |
|---|---|---|---|---|
| 4 | 54 | 17 | 84 | 327 mm |
| 6 | 34 | 6 | 76 | 24 mm |
| 8 | 29 | 9 | 69 | 30 mm |
The evidence for 6 is routing difficulty. At 4 layers the router has to cut 327 mm through copper the photos show; at 6 that falls to 24 mm, and 8 adds nothing. Routing the same stackup again varies by about a quarter (6 layers: 25 to 34 open), so 6 and 8 are not distinguishable on open connections. The photos prove no minimum: the 3 vias read as leading only inward look like ordinary domes in a stitching field. The layer count has not been seen directly: T-layers settles it.
The open connections are a rules limit more than a layer limit. The same copy routed at JLC 4-layer capabilities (0.127 mm track and clearance, 0.45/0.2 mm via) leaves 30 open at 4 layers and 2 at 6. KiCad's shared service checks only its default rules, so that run has no valid DRC. It is in routes-experiment-jlc.
Inner layers proposed: In1 GND, In4 +3V3 (both INFERRED, as the largest power nets), In2 and In3 signals. The routed copper is one possible way to make the connections, not what is inside the board.
Confidence (last review pass)
| Category | Level | Why |
|---|---|---|
| identity | Medium | DRV8323S, SS210 diodes, R002 shunts, the 100 uH inductor and every connector are read off the photo; the MOSFETs, the STM32G4 variant, the buck IC and the CAN transceiver rest on package and circuit role |
| values | Medium | Resistor codes read where legible; every MLCC value and ten resistor codes are not readable |
| blocks | High | Silkscreen labels and part identities agree with the block topology |
| placement | High | 103 of 137 parts placed by their own pads on the photo; 62 courtyard overlaps and 23 pad-to-pad clearance errors remain |
| copper | Medium | Phase, VIN and ground pours and the via fields follow the photos by eye. See the misses below |
| vias | Medium at the last pass, too high | Up to 338 of the 1028 land on pale pixels, mostly silkscreen letters and lines, and look false. Only 45 are confirmed on both faces, because vias tent on the top. Sizes are the rule's, not measured |
| layers | Medium | From routing difficulty. Never seen directly |
| connectivity | Low | The ring test does not reliably separate a joined plated pad from an isolated one on these photos; 827 mm2 of pour and 94 mm of track have no net; the MCU pin map and passive roles are inferred |
Not done
- 34 connections stay open at 6 layers, and KiCad reports 76 missing, because some seen copper of one net is not joined in the copy.
- The bottom's upper-left rails are largely missing from the copy. The photo is darker there and the islands fragment.
- The bottom's signal bundles come out mostly as gaps in the pour, not separate tracks. 637 short fragments were dropped as misreadings.
- False vias. Up to 338 kept vias sit on silkscreen or other pale pixels. They feed net assignment and block the router, so the net and layer results are less certain than the tables suggest.
- The router does not yet claim copper of unknown net. It pays to cross it where it could be following it.
- Refilling zones in KiCad will flood the traced pours; the written fill is the measured one.
Grading against the 2026-11-02 hand-made reverse engineering (reference only, not input)
That earlier work is not the truth either, so agreement shows only that two readings match.
- 96 percent of the earlier board's parts matched by position, median offset 0.46 mm, 110 rotations agree.
- 86 percent of the pin pairs this run puts on one net share a net there too (weighted by the large GND and VIN nets).
- Layer count differs: 6 here, 4 there. The earlier board's 4 left 27 nets to route by hand, so it did not close either.
- Disagreements to settle with the tests: the gate-driver passives (0805 here, 0603 there), the JST connector position, four small plated holes found only here.
# Driver board: reverse engineered from photos
Run of adom-aiflow-reverse 0.2 on Driver1.JPG to Driver4.jpg only, updated 2026-11-04. The generated tables (evidence counts, every open item, the tests) are in report-tables.md.
**Result: a 6-layer proposal, with copper traced from the photos on both faces. No stackup closes every connection at KiCad default rules, so this is not a finished board.** 34 of 249 connections stay open at 6 layers, nearly all fan-outs at the two QFNs.
## What the board is
A three-phase BLDC motor controller, 73.65 x 61.78 mm with 2.5 mm corners. A TI DRV8323S gate driver (marking read, confirmed against TI's product page) drives six TDSON-8 MOSFETs in three half-bridges to the X1, X2 and X3 lugs, with 2 mΩ shunts (R002) on the low sides. An STM32G4 (silkscreen; package marking unreadable) controls it. Logic power comes through a Schottky (SS210) from VIN into an 8-pin SOT-23 buck with a 100 µH inductor, then two adjustable SOT-223 regulators whose dividers give 4.48 V and 3.28 V. The board also has CAN (SOIC-8 transceiver, terminal blocks, header, termination jumper), an AUX port, an SPI or I2C expansion header, a 4-pin fan header, a motor NTC input, SWD and a reset button.
## How it was measured
| Step | Result |
|---|---|
| Photos | Outline found in all four photos (connectors over the edge left out of the fit); bottom turned over top-to-bottom (38 holes agree, 2 disagree) |
| Scale | 46.599 px/mm from the 2.0 and 2.54 mm header rows. The DRV8323S body (6 x 6 mm, TI; it measures 41 px/mm) only picks the pitch standard, so the number rests on the holes alone. Bottom aligned to top on 40 holes, 0.204 mm residual |
| 1 Parts | 137 parts. 103 placed by their own pads on the photo, 12 from a body or plated-hole centre, the rest by direct reading. 673 detected candidates all accounted for |
| 2 Blocks | 11 blocks from silkscreen and topology |
| 3 Copper | 1444 islands read from the photos: 116 pours and 314 tracks on the board, 1028 vias kept of 2681 candidates, up to 338 of them likely false, on silkscreen or other pale pixels |
| 4 Copy | KiCad board with the traced pours filled as photographed. 146 DRC errors before routing: 62 courtyard overlaps, 59 clearance, 30 board edge, 3 solder mask bridge, 1 hole in a courtyard |
| 5 Connections | 77 nets, completed from TI SLVSDJ3D (DRV8323S pins), KiCad's ST-derived STM32G431 symbol and inference. 99 pins disagree with the copper they appear to touch and are reported, not applied |
| 5 Layers | **6 proposed.** See below |
| 6 Review | 4 passes; the last changed nothing |
| 7 Tests | 119 tests covering the open items |
## Layer count
Rules: KiCad default (0.2 mm track and clearance, 0.6/0.3 mm via, 0.5 mm edge), set at the start and used by the zones, router and DRC.
| Layers | Open of 249 | New DRC errors | Missing per KiCad | Crossing seen copper |
|---|---|---|---|---|
| 4 | 54 | 17 | 84 | 327 mm |
| **6** | **34** | **6** | **76** | **24 mm** |
| 8 | 29 | 9 | 69 | 30 mm |
The evidence for 6 is routing difficulty. At 4 layers the router has to cut 327 mm through copper the photos show; at 6 that falls to 24 mm, and 8 adds nothing. Routing the same stackup again varies by about a quarter (6 layers: 25 to 34 open), so 6 and 8 are not distinguishable on open connections. The photos prove no minimum: the 3 vias read as leading only inward look like ordinary domes in a stitching field. The layer count has not been seen directly: T-layers settles it.
The open connections are a rules limit more than a layer limit. The same copy routed at JLC 4-layer capabilities (0.127 mm track and clearance, 0.45/0.2 mm via) leaves 30 open at 4 layers and **2 at 6**. KiCad's shared service checks only its default rules, so that run has no valid DRC. It is in routes-experiment-jlc.
Inner layers proposed: In1 GND, In4 +3V3 (both INFERRED, as the largest power nets), In2 and In3 signals. The routed copper is one possible way to make the connections, not what is inside the board.
## Confidence (last review pass)
| Category | Level | Why |
|---|---|---|
| identity | Medium | DRV8323S, SS210 diodes, R002 shunts, the 100 uH inductor and every connector are read off the photo; the MOSFETs, the STM32G4 variant, the buck IC and the CAN transceiver rest on package and circuit role |
| values | Medium | Resistor codes read where legible; every MLCC value and ten resistor codes are not readable |
| blocks | High | Silkscreen labels and part identities agree with the block topology |
| placement | High | 103 of 137 parts placed by their own pads on the photo; 62 courtyard overlaps and 23 pad-to-pad clearance errors remain |
| copper | Medium | Phase, VIN and ground pours and the via fields follow the photos by eye. See the misses below |
| vias | Medium at the last pass, too high | Up to 338 of the 1028 land on pale pixels, mostly silkscreen letters and lines, and look false. Only 45 are confirmed on both faces, because vias tent on the top. Sizes are the rule's, not measured |
| layers | Medium | From routing difficulty. Never seen directly |
| connectivity | Low | The ring test does not reliably separate a joined plated pad from an isolated one on these photos; 827 mm2 of pour and 94 mm of track have no net; the MCU pin map and passive roles are inferred |
## Not done
- **34 connections stay open at 6 layers**, and KiCad reports 76 missing, because some seen copper of one net is not joined in the copy.
- **The bottom's upper-left rails are largely missing** from the copy. The photo is darker there and the islands fragment.
- **The bottom's signal bundles** come out mostly as gaps in the pour, not separate tracks. 637 short fragments were dropped as misreadings.
- **False vias.** Up to 338 kept vias sit on silkscreen or other pale pixels. They feed net assignment and block the router, so the net and layer results are less certain than the tables suggest.
- **The router does not yet claim copper of unknown net.** It pays to cross it where it could be following it.
- **Refilling zones in KiCad** will flood the traced pours; the written fill is the measured one.
## Grading against the 2026-11-02 hand-made reverse engineering (reference only, not input)
That earlier work is not the truth either, so agreement shows only that two readings match.
- 96 percent of the earlier board's parts matched by position, median offset 0.46 mm, 110 rotations agree.
- 86 percent of the pin pairs this run puts on one net share a net there too (weighted by the large GND and VIN nets).
- Layer count differs: 6 here, 4 there. The earlier board's 4 left 27 nets to route by hand, so it did not close either.
- Disagreements to settle with the tests: the gate-driver passives (0805 here, 0603 there), the JST connector position, four small plated holes found only here.