# Raspberry Pi Compute Module 5: reverse engineered from photos

Run 6 of adom-aiflow-reverse (branch test/cm5-photos, commit 0a241f6) on ten photos of one CM5, 2026-11-10. The generated tables (evidence counts, every open item, the tests) are in report-tables.md.

**Result: both outer faces read from the photos, with 258 parts, 883 vias and 2,306 pieces of copper. This is not a finished board, and the 90 percent confidence target was not reached.**

Overall confidence: 0.0 of 100, target 90: STALLED

Overall is the lowest category. Blocks and connectivity score 0: no block is confirmed by anything seen on the board, and KiCad finds 499 pieces of ground copper not joined to each other, because the copy has no inner layers.

## What the board is

A Raspberry Pi Compute Module 5, 55 x 40 mm. Read from the markings: a Broadcom BCM2712 processor under a metal lid, an RP1 I/O controller, a Broadcom BCM54210PE Ethernet PHY, a Renesas DA9091 power chip, and a 54 MHz crystal. A memory package sits beside the processor; its marking is only partly legible and the size (4 GB) is taken from the strap fitted in the silkscreen table. Two 100-pin connectors on the bottom face go to the carrier board. The radio module is not fitted on this unit.

## Where each kind of information came from

| Information | Source |
|---|---|
| Parts, positions, copper, vias, silkscreen, outline | The ten photos only |
| Scale | Photos, with the board size and hole spacing (55 x 40 mm, holes 48 x 33 mm) from the Raspberry Pi CM5 datasheet |
| Names of 142 connector nets | Raspberry Pi CM5 datasheet, Table 4 pinout. Each net cites it |
| Layer count of 10 | Raspberry Pi's published statement that the CM5 is a ten-layer board. Routing could not tell |
| A public CT scan of another CM5 | Used only to check the work afterwards; not an input to this run |

## How it was measured

| Step | Result |
|---|---|
| Photos | Ten close-ups stitched into one image per face, bottom turned over onto the top through the four mounting holes |
| Scale | Working frame 40 px/mm. A 0.1 mm track is 4 pixels wide, which limits the copper and via readings below |
| Parts | 258 parts: 41 read by eye from the close-ups (chips, crystals, inductors, connectors, holes, marks), 217 chip passives found by the flow's body-first reader. 140 placed by a program measurement, 118 by the reading. 50 chip parts had their size class changed by how their pads fit the photo's metal |
| Blocks | 8 blocks by position, all inferred |
| Copper | 721 pours and 1,585 tracks read from the photos. 44 false islands on chip markings and the processor lid are left out |
| Vias | 883 kept. 15 candidates dropped: 9 second looks at a kept via, 5 in silkscreen print, 1 on a pad |
| Against the photos | Held-out copper IoU: top 0.698, bottom 0.749. The fidelity check fails its 0.8 limit on several layers |
| Nets | 192 nets: 21 measured, 171 inferred. 142 of 337 pins seen on their net |
| Review | 5 passes, STALLED |
| Tests | 451 tests covering 1,602 open items |

## How each piece of copper got its net

| Evidence | Area | Track length | Vias |
|---|---|---|---|
| A pad touches it | 84.1% | 66.5% | 69.1% |
| Through a via | 5.0% | 6.5% | 2.5% |
| Inferred | 0.3% | 0.9% | 0.5% |
| Net group only | 0.3% | 5.7% | 1.5% |
| No net | 10.4% | 20.5% | 23.6% |
| Conflict | 0.0% | 0.0% | 2.9% |

"Every piece of copper on a net" is not met: 714 of 1,469 pieces have no net. Most named copper is ground. A name here means the copper touches a pad of that net in the photo; it does not mean the net is complete.

## Layer count

| Layers | Open | New DRC errors | Missing per KiCad |
|---|---|---|---|
| 2 | 42 of 59 | 409 | 499 |
| 4 | 42 of 59 | 2,322 | 499 |
| 6 | 42 of 59 | 371 | 499 |
| 8 | 42 of 59 | 345 | 499 |
| 10 | 42 of 59 | 394 | 499 |

Routing says nothing about the layer count on this board: every stackup leaves the same 42 connections open, because their pins are under ball grid packages or their copper runs on inner layers no photo shows. The count of 10 is Raspberry Pi's own statement. No inner copper is drawn, so all 499 missing connections KiCad reports are ground pieces on the outer faces that the real board joins through inner planes.

In runs 3 and 5 the KiCad check service was unreachable at 6 layers and above, and the program counted that as 0 errors and 0 missing connections. That is corrected: a check that did not run now reads as unknown and the layers check fails on it.

## Confidence by category

Scores come from independent audits and measurements. No score is typed. Four auditors who did not produce the run judged random crops with false claims planted among them. Every planted claim was rejected, so no sample was voided.

| Category | Score | Limited by |
|---|---|---|
| Placement | 54.2 | 118 parts placed by a reading, not a program measurement. The audit gave 41 of 47 correct; the 6 faults are five size classes too large and one part skewed |
| Vias | 40.0 | Capped: no layer score for vias against the photos. The audit gave 43 of 51 kept vias real and 5 of 6 dropped candidates correctly dropped |
| Copper | 39.1 | Audit: 35 of 51 points stated as copper and 26 of 50 stated as bare board judged correct. Most errors are at fine tracks, gap lines and pour edges |
| Layers | 28.8 | 42 of 59 connections stay open at 10 layers; the count itself is from an outside statement |
| Identity | 4.6 | 12 of 258 parts have a marking that was read. Chip passives carry no marking |
| Values | 2.3 | 6 of 254 values read |
| Blocks | 0.0 | All 8 blocks are inferred from position |
| Connectivity | 0.0 | KiCad finds 499 missing connections against 145 expected. The audit gave 27 of 39 pad-to-copper joins and 31 of 52 copper joins correct; 201 of 298 pins and 433 of 2,306 islands show no join in the photos and count as not correct |

The connectivity audit no longer asks whether a pin "is on net X", which no photo can show. Each claim states one join between two marked things. No claim in the audit checks a net name: the 142 names taken from the datasheet pinout rest on the datasheet alone.

## What changed in the program during this run series

Run 3 on the same photos scored 43 of 98 on placement and its via and copper samples were incomplete or void. The faults were in the program, so the program was changed and the run repeated from the photos:

| Fault found by the audits | Change | Checked how |
|---|---|---|
| Passive parts paired across neighbours | Body-first passive reader inside `detect parts` | Placement 43 of 98, then 39 of 47, then 41 of 47 |
| Snap moved small parts up to 0.95 mm onto neighbours | Reach tied to the part's own size | Median move now 0.04 mm |
| Real vias beside pads dropped | Kept when the photo shows board all round; each drop listed with its reason | Vias kept 636, then 883 |
| Chip markings read as copper | Nothing on a part's top is copper | 44 false islands gone, other zones unchanged |
| Chip parts one size too large | Size chosen by pad fit | Fixes 6 of 8 named cases in run 5 |
| Vias read in silkscreen print | Dropped when seen on one face only and lying in print | All 5 such drops confirmed by the auditor |
| Audit claims no photo could settle | Claims reworded as joins; unproven items count against the score | 15 of 101 "cannot tell", was 54 of 110 |
| Unreachable check counted as zero | Counted as unknown | See Layer count |

Two later changes are in the program but not in this run and not audited: ties in pad fit go to the smaller size, and passive angles go to the nearest 45 degrees. The passive reader's colour thresholds were read from these photos; on the Driver board's darker photo it finds few parts and invents some. The Driver board has not been rerun or re-audited on this program.

## What it would take to reach 90

Photos alone cannot get there on this board. Identity and values need a bill of materials or meter readings: 217 of the parts are unmarked passives. Blocks need the schematic or probing. Connectivity needs the inner layers, from X-ray or CT, and continuity measurements for the pins under the ball grid packages. Copper and vias need a higher working resolution than 40 px/mm, and the via reader needs to reject dark spots that have no ring.