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AI Flow: Reverse Engineering
Public Made by Adomby adom
Photos of a PCB to a tagged KiCad copy: parts placed, copper and nets with their evidence, a schematic, a measured confidence score, bench tests and a video of the run.
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Caleb
Add the Compute Module 5 run of version 0.4.0: report, evidence images, audit sheets and KiCad copy
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{
"candidates": [
{
"connections": 59,
"drcErrors": 409,
"drcTypes": {
"clearance": 264,
"hole_clearance": 81,
"shorting_items": 33,
"solder_mask_bridge": 31
},
"inheritedErrors": 727,
"kicadOpen": 499,
"layerUse": [
{
"layer": "F.Cu",
"plane": null,
"trackMm": 0.5
},
{
"layer": "B.Cu",
"plane": null,
"trackMm": 9.8
}
],
"layers": 2,
"log": "reverse-flow/routes/L2/route.log",
"narrowedPower": [
"GND",
"+5V"
],
"open": 42,
"passes": 3,
"planes": [],
"ripups": 0,
"rules": "kicad-default",
"run": "reverse-flow/routes/L2",
"seconds": 12.1,
"seenCrossingMm": 0.3,
"seenTracksDisplaced": 7,
"stop": "2 passes closed nothing new: this stackup is the limit",
"trackMm": 10.3,
"vias": 0
},
{
"connections": 59,
"drcErrors": 2322,
"drcTypes": {
"annular_width": 199,
"clearance": 499,
"copper_edge_clearance": 199,
"courtyards_overlap": 196,
"drill_out_of_range": 199,
"hole_clearance": 199,
"npth_inside_courtyard": 4,
"padstack_invalid": 22,
"pth_inside_courtyard": 3,
"shorting_items": 199,
"solder_mask_bridge": 205,
"track_width": 199,
"via_diameter": 199
},
"inheritedErrors": 0,
"kicadOpen": 499,
"layerUse": [
{
"layer": "F.Cu",
"plane": null,
"trackMm": 0.2
},
{
"layer": "In1.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In2.Cu",
"plane": null,
"trackMm": 0.8
},
{
"layer": "B.Cu",
"plane": null,
"trackMm": 9.8
}
],
"layers": 4,
"log": "reverse-flow/routes/L4/route.log",
"narrowedPower": [
"GND",
"+5V"
],
"open": 42,
"passes": 3,
"planes": [],
"ripups": 0,
"rules": "kicad-default",
"run": "reverse-flow/routes/L4",
"seconds": 12.4,
"seenCrossingMm": 0.2,
"seenTracksDisplaced": 3,
"stop": "2 passes closed nothing new: this stackup is the limit",
"trackMm": 10.7,
"vias": 0
},
{
"connections": 59,
"drcErrors": 371,
"drcTypes": {
"clearance": 237,
"hole_clearance": 68,
"shorting_items": 33,
"solder_mask_bridge": 33
},
"inheritedErrors": 696,
"kicadOpen": 499,
"layerUse": [
{
"layer": "F.Cu",
"plane": null,
"trackMm": 0.2
},
{
"layer": "In1.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In2.Cu",
"plane": null,
"trackMm": 0.8
},
{
"layer": "In3.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In4.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "B.Cu",
"plane": null,
"trackMm": 9.8
}
],
"layers": 6,
"log": "reverse-flow/routes/L6/route.log",
"narrowedPower": [
"GND",
"+5V"
],
"open": 42,
"passes": 3,
"planes": [],
"ripups": 0,
"rules": "kicad-default",
"run": "reverse-flow/routes/L6",
"seconds": 10.0,
"seenCrossingMm": 0.2,
"seenTracksDisplaced": 3,
"stop": "2 passes closed nothing new: this stackup is the limit",
"trackMm": 10.7,
"vias": 0
},
{
"connections": 59,
"drcErrors": 345,
"drcTypes": {
"clearance": 247,
"hole_clearance": 54,
"shorting_items": 23,
"solder_mask_bridge": 21
},
"inheritedErrors": 693,
"kicadOpen": 499,
"layerUse": [
{
"layer": "F.Cu",
"plane": null,
"trackMm": 0.2
},
{
"layer": "In1.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In2.Cu",
"plane": null,
"trackMm": 0.8
},
{
"layer": "In3.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In4.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In5.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In6.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "B.Cu",
"plane": null,
"trackMm": 9.8
}
],
"layers": 8,
"log": "reverse-flow/routes/L8/route.log",
"narrowedPower": [
"GND",
"+5V"
],
"open": 42,
"passes": 3,
"planes": [],
"ripups": 0,
"rules": "kicad-default",
"run": "reverse-flow/routes/L8",
"seconds": 10.4,
"seenCrossingMm": 0.2,
"seenTracksDisplaced": 3,
"stop": "2 passes closed nothing new: this stackup is the limit",
"trackMm": 10.7,
"vias": 0
},
{
"connections": 59,
"drcErrors": 394,
"drcTypes": {
"clearance": 256,
"hole_clearance": 58,
"shorting_items": 34,
"solder_mask_bridge": 46
},
"inheritedErrors": 688,
"kicadOpen": 499,
"layerUse": [
{
"layer": "F.Cu",
"plane": null,
"trackMm": 0.2
},
{
"layer": "In1.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In2.Cu",
"plane": null,
"trackMm": 0.8
},
{
"layer": "In3.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In4.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In5.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In6.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In7.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "In8.Cu",
"plane": null,
"trackMm": 0.0
},
{
"layer": "B.Cu",
"plane": null,
"trackMm": 9.8
}
],
"layers": 10,
"log": "reverse-flow/routes/L10/route.log",
"narrowedPower": [
"GND",
"+5V"
],
"open": 42,
"passes": 3,
"planes": [],
"ripups": 0,
"rules": "kicad-default",
"run": "reverse-flow/routes/L10",
"seconds": 10.7,
"seenCrossingMm": 0.2,
"seenTracksDisplaced": 3,
"stop": "2 passes closed nothing new: this stackup is the limit",
"trackMm": 10.7,
"vias": 0
}
],
"escalation": "not closed; last: 10 layers: 42 open, 394 new DRC errors, 499 missing per KiCad (2 passes closed nothing new: this stackup is the limit)",
"proposed": 10,
"tag": "DATASHEET",
"tests": [
"T-layers"
],
"trail": [
"2 layers: 42 of 59 connections open, 409 new DRC errors, 0 vias, 10 mm of track, 0 mm crossing seen copper",
"4 layers: 42 of 59 connections open, 2322 new DRC errors, 0 vias, 11 mm of track, 0 mm crossing seen copper",
"6 layers: 42 of 59 connections open, 371 new DRC errors, 0 vias, 11 mm of track, 0 mm crossing seen copper",
"8 layers: 42 of 59 connections open, 345 new DRC errors, 0 vias, 11 mm of track, 0 mm crossing seen copper",
"10 layers: 42 of 59 connections open, 394 new DRC errors, 0 vias, 11 mm of track, 0 mm crossing seen copper"
],
"why": "Routing cannot tell the layer count here (see routingSaid). Raspberry Pi states the CM5 is ten layers. Seen in the photos: through vias pair across the faces and many vias show on one face only, so there are blind or buried vias. The public CT scan of another CM5 resolves at least 5 internal planes. Taken from the outside source, not measured.",
"routingSaid": "every stackup tried leaves the same 42 of 59 connections open: more layers changed nothing, so the open ones are blocked by something else (hidden pins, missing footprints) and routing cannot tell the layer count. Measure the layers (cross-section, CT, or the edge under a microscope)",
"source": "Raspberry Pi, \"Meet the engineer: Dominic Plunkett on Compute Module 5\" (raspberrypi.com/news, fetched 2026-11-07): the CM5 is a ten-layer circuit board",
"openNote": "42 of 59 known connections stay open at every layer count tried (2, 4, 6, 8, 10). They are open because their pins are hidden or their path is not visible: ball grid array pins under U1, U2 and U3, and connector pins named from the datasheet pinout whose copper runs on inner layers. More layers do not close them, so the route cannot settle the layer count; the count of 10 is from Raspberry Pi's published statement. Each open connection is listed in tests.json for a continuity check on the bench."
}