# Status

Verified on one board: the Driver motor controller (Driver 1 to 4 photos, 2026-11-04), rules `kicad-default`. A second board, the Compute Module 5, was run as far as `check fidelity` from public photos, in its own section below. Nothing here has been checked against a real netlist, stackup or X-ray.

## 0.4.0 (2026-11-10)

Second board: a Raspberry Pi Compute Module 5 from ten photos, run to the end of the flow ([runs/cm5-run6](../runs/cm5-run6/README.md)). Overall confidence 0.0 of 100, STALLED. What changed in the program is listed in the README. The Driver sections below describe 0.3.0; the Driver has not been run to completion or audited on 0.4.0.

Known gaps added by this version:

- The body-first passive reader uses colour thresholds read from the CM5 photos. On the Driver's darker photo it found 20 passives, 4 of them invented, and missed most of the board. Its candidates are proposals; check them by eye. Thresholds relative to each photo are the fix.
- On the Driver, the changed snap reach lands 7 of 123 parts more than 0.3 mm from where 0.3.0 put them. Which position is right has not been checked.
- The via reader accepts dark spots with no ring: 8 of 51 sampled kept vias on the CM5 were false.
- Copper on the CM5 is right at about 60% of audited points. A 0.1 mm track is 4 pixels wide in the 40 px/mm working frame.
- No audit claim checks a net name any more. A pin or island with a correct local join on a wrong net scores as correct; named pins with no visible join are only counted against the figure.
- Planted copper claims go one way only on the CM5 (copper stated as bare), so an auditor who answers ok to every copper claim is not caught. The tool says so at draw time.
- An inferred inner plane does not close ground pieces in KiCad's count: the CM5 copy shows 499 missing connections at ten layers.
- Routing still takes most of a run when no stackup closes.

Verified on one board only: the Driver motor controller (Driver 1 to 4 photos), rules `kicad-default`, version 0.3.0, run of 2026-11-06. **Not finished, and the 90 percent confidence target was not reached:** the loop answers STALLED at an overall 0.0, because overall is the lowest category.

## What it does on that board

| Measure | Result |
|---|---|
| Parts placed | 137, 103 by their own pads on the photo |
| Copper traced | Read pixel by pixel on both faces, every island accounted for in `detect/copper-island-accounting.json` |
| Vias kept | 1317, all read on the bottom photo. Held-out sample of 220 labelled by eye: precision 0.97, recall 0.92 (before: 0.40, 0.38). A fresh 150 of the kept list: 141 real, 4 false, 5 cannot tell |
| Copy's own DRC, unrouted | 146 errors: 62 courtyard overlaps, 59 clearance, 30 edge, 3 solder mask bridge, 1 hole in a courtyard |

| Layers | Open of 249 | New DRC errors | Missing per KiCad | Vias added | Track mm | Crossing seen copper, mm |
|---|---|---|---|---|---|---|
| 4 | 54 | 17 | 84 | 210 | 1002 | 327 |
| 6 (proposed) | 34 | 6 | 76 | 230 | 1165 | 24 |
| 8 | 29 | 9 | 69 | 215 | 1187 | 30 |

Routing the same stackup again varies: 6 layers left 25 to 34 open across runs.

With the JLC 4-layer capabilities (0.127 mm track and clearance, 0.45/0.2 mm via), the same copy leaves 30 open at 4 layers and 2 at 6, crossing 385 mm and 39 mm. The open connections at default rules are almost all QFN fan-outs, so they are mainly a rules limit. KiCad's shared service checks only its default rules, so that run's DRC counts do not apply: its gate needs a native `kicad-cli`.

## Checked against the real design

The true design (found by the owner's request) was kept outside the flow as a sealed answer key: never an input, never shown to an agent, totals only, every attempt logged, and the scorer locked by hash (`edf583a6419b9d9d`). Thresholds were not tuned from item-level comparison.

| Measure | 0.2.0 | 0.3.0 |
|---|---|---|
| Vias that are real | 42.4% | 95.5% |
| Design vias found | 25.8% | 75.2% |
| Outline error, x / y | -0.35 / -0.22 mm | 0.04 / 0.03 mm |
| Copper match (IoU), top / bottom | 61.4 / 80.2% | 67.4 / 88.9% |
| Copper recall, top / bottom | 67.1 / 85.9% | 72.6 / 92.7% |
| Copper precision, top / bottom | 87.9 / 92.4% | 90.4 / 95.6% |
| Copper net purity, top / bottom | 70.5 / 77.5% | 76.1 / 85.9% |
| Copper net completeness, top / bottom | 70.4 / 88.4% | 69.7 / 83.3% |
| Copper with no named net, top / bottom | 10.7 / 1.9% | 13.8 / 5.9% |
| Pins on a consistent net | 45.8% | 48.4% |
| Pin pairs, precision / recall | 18.5 / 29.8% | 20.3 / 33.3% |
| Parts found / placed parts real | 84.7 / 97.1% | 84.7 / 96.4% |
| Median part offset | 0.107 mm | 0.125 mm |
| Part values matching | 3.0% | 3.0% |
| Layer proposal | 6, correct | 6, correct |

**Limits on this check.** The true layer count and outline were known while working, so neither result is blind. One scale hint given to the layers agent was slightly informed by the key. An earlier rule change selecting 6 was made before the key was opened. The scorer counts copper hidden under parts, which no photo can show, so 100 percent is out of reach, and its pin matching has not been audited. Value agreement is probably understated by empty values and format differences. The thresholds came from this board.

## Connectivity on that board

Measured by `connect attribute` at commit `cdc9d4f`, against the loop 2 start. All figures from the Driver photos only.

| Measure | Before | After |
|---|---|---|
| Nets, all tagged INFERRED | 77 | 77 |
| Pins seen on their net (solid contact, named copper) | 91 of 397 | 77 of 397 |
| Pieces into conductors | 2191 pieces, no stitching | 2188 into 1731, by 628 stitches |
| Track length: copper, via, inferred, group, none, conflict % | 8.6, 2.5, 8.5, 14.3, 64.6, 1.6 | 30.1, 6.3, 4.1, 11.6, 47.6, 0.4 |
| Vias: copper, via, inferred, group, none, conflict % | 35.8, 18.7, 13.2, 14.9, 14.0, 3.4 | 57.5, 10.3, 15.4, 3.3, 7.9, 5.6 |
| Pour area: copper, via, inferred, group, none, conflict % | 46.6, 22.2, 10.8, 9.8, 8.2, 2.3 | 76.0, 7.8, 7.5, 1.9, 6.8, 0.0 |
| Apparent shorts listed | 29 | 14 |

"Before" counts 91 pins partly because its ring test passed false pad joins, so the fall is not a loss of the same evidence.

**Held-out check.** 150 pad-to-pad connections plus 11 controls, drawn by `tools/connect_sample.py` (seed b370454dd3e0ed2e) after the method was frozen, excluding the tuning sample. Three independent readers judged crops with no net names. All 11 controls were rejected or left open. `solid` is what names rest on; `unsettled` has a pad whose edge did not settle it.

| Grade | n | ok | wrong | cannot tell | ok / all, Wilson lower 95% | ok / judged, Wilson lower 95% |
|---|---|---|---|---|---|---|
| solid, big conductors | 10 | 4 | 0 | 6 | 40%, 17% | 100%, 51% |
| solid, small conductors | 33 | 22 | 5 | 6 | 67%, 50% | 81%, 63% |
| unsettled, big | 65 | 15 | 13 | 37 | 23%, 15% | 54%, 36% |
| unsettled, small | 42 | 13 | 6 | 23 | 31%, 19% | 68%, 46% |
| all solid | 43 | 26 | 5 | 12 | 60%, 46% | 84%, 67% |
| all | 150 | 54 | 24 | 72 | 36%, 29% | 69%, 58% |

**This is not 90.** The wrong solid cards include three of the four pins moved by the copper: C33.2, R11.1 and Q1.5. Treat `pinsMoved` as things to look at, not as corrections. U1 and U2 mostly stay hidden or unsettled: 11 pins of 90 have a solid contact.

## Confidence on that board

Computed by `confidence` from the 0.2.0 files, target 90. Overall is the lowest category: **21.4**. No target met: `check review` fails.

| Category | Score | What limits it |
|---|---|---|
| identity | 40.0 | no audit done |
| values | 34.3 | 47 of 137 stated values tagged as seen |
| blocks | 40.0 | no audit done |
| placement | 40.0 | no audit done; no `fidelity.json` |
| copper | 40.0 | no audit done; no `fidelity.json` |
| vias | 40.0 | no `fidelity.json`; audit bound 41.7 |
| connectivity | 21.4 | 68 of 317 connections joined by seen copper |
| layers | 30.0 | photos never show an inner layer |

The via audit is one auditor judging 114 crops by eye (seed 179b5abec06c3269), with all 11 planted claims rejected: 28 of 51 kept vias real, 22 false, 1 unclear, and 7 of 52 dropped candidates real, 2 unclear.

## The visible layers against the photos

`check fidelity` writes `reverse-flow/fidelity.json` and `evidence/fidelity-*.jpg` (green both, red board only, cyan photo only, purple excluded). See method.md for what each sample means. The classifier that scores silk and metal also traces them, so the primary-photo silk figures are close to self-agreement. Read the second-photo and edge figures for those layers.

| Layer | IoU before | IoU after, held-out tiles | Second photo | Boundary after, median / p95 mm | Excluded mm² |
|---|---|---|---|---|---|
| F.SilkS | 0.046 | 0.983 | 0.742 | 0 / 0.025 | 1146 |
| B.SilkS | 0.000 | 0.979 | 0.740 | 0 / 0.025 | 60 |
| F.Mask opening | 0.564 | 0.824 | 0.715 | 0 / 0.85 | 1087 |
| B.Mask opening | 0.584 | 0.906 | 0.838 | 0 / 1.225 | 0 |
| F exposed metal | 0.476 | 0.789 | 0.674 | 0 / 0.55 | 1087 |
| B exposed metal | 0.417 | 0.828 | 0.753 | 0 / 0.4 | 0 |
| F holes | 0.640 | 0.920 | 0.864 | 0.025 / 0.05 | 1322 |
| B holes | 0.394 | 0.758 | 0.746 | 0.025 / 7.9 | 23 |
| F.Cu | see below | 0.826 | 0.813 | 0.05 / 0.375 | 2363 |
| B.Cu | see below | 0.871 | 0.880 | 0.058 / 1.233 | 597 |

Board area 4544 mm². "Before" is the published board against its own unregistered frame.

**Copper, with one scorer.** The copper scorer was wrong until this round (method.md), so earlier copper figures cannot be compared with these. All on the repaired scorer, without routed copper, held-out tiles then second photo:

| Board | F.Cu | B.Cu |
|---|---|---|
| Before this reader | 0.835, 0.815 | 0.841, 0.844 |
| This reader, primary photo only | 0.829, 0.810 | 0.870, 0.877 |
| This reader, both photos | 0.826, 0.813 | 0.871, 0.880 |

The second-photo figure on the both-photos row is not independent. The primary-only row is the fair test of the method. **The top did not improve**, and the second photo adds nothing to these figures. The two photos of a face agree with each other at 0.927 and 0.948, which is the ceiling. The scorer still reads shadow stripes in dense dome fields, so it understates the bottom.

Kept domes in held-out tiles with a small hole within 0.5 mm: 396 of 726 before, 68 of 726 now. Eye labels from the earlier round, held-out set: bottom coverage 0.916 to 0.952 and false coverage 0.258 to 0.315 (40 laminate labels), top 0.869 to 0.889 and 0.124 to 0.137 (45 laminate labels). Those false-coverage ranges are too wide to say it moved.

The photos can show copper on 48 percent of the top and 87 percent of the bottom. The rest is under part bodies, silk, metal and holes, or within 6 px of them.

KiCad's plot against the copper as read, over visible area: F.Cu 0.970 to 0.972, B.Cu 0.968 to 0.981. Over the whole board, 0.82 to 0.83 and 0.96 to 0.97, where the top's shortfall is pads the read layer does not draw.

**DRC.** 2411 violations, 1578 errors, 499 unconnected, against 3119, 2164 and 419 before (that board had routed copper in it). KiCad stops most types at 199, so several counts are lower bounds. Split by rule: 655 are photographed geometry at default rules (gaps from 0.075 to 0.2 mm, tracks from 0.1 to 0.2 mm, copper within 0.5 mm of the edge, close holes), 1485 are errors in the copy (shorts, dangling items, isolated copper, gaps under 0.075 mm, mask bridges, hole clearance), and 271 are silk, courtyards and library. Via diameter and drill errors are gone, and annular errors fell from 199 or more to 8.

**What limits the figures.** The second-photo silk figure matches the photo against itself (0.744 and 0.739), so it measures thin lines going soft between two shots and glints passing the colour test, not the drawing. Edges sit 0.025 mm from the steepest luminance edge at the median, 0.14 mm at the 95th percentile.

**Scale and distortion, from the photos alone.**

- Bottom against top: up to 0.58 mm before registration, 0.026 mm RMS leaving each hole out.
- Hole rows against library pitch: the frame draws 0.10% long in x (3 rows, spread 0.04%) and 0.37% long in y (3 rows, spread 0.19%). That is about 0.17 mm of x/y mismatch over the board's height.
- Shear: the right edge leans 4.7 mrad in the top frame, about 0.29 mm over its length. Fitted corners were off by several pixels. The top frame was not changed, because parts.json is measured in it.
- Lens: edges bow by 0.04 mm or less, so lens distortion is not the main error.
- Outline: 73.76 x 62.02 mm with 3.08 mm corners, against 73.65 x 61.78 mm and 2.5 mm before. The pitch standard is confirmed independently: U1's 0.5 mm pins read about 1% off at 46.6 px/mm, and would be 13% off at 41.
- Small pads are poor rulers: their ratios spread 1.6% to 2.5%.

**Not yet right.** A through pad has one outline for both faces, so the face it was not taken from is off by about 0.1 mm. QFN pins smaller than the metal test stay library shapes. Photographed pads reach traced copper that the library shapes cleared, which adds DRC errors. The X1, X2 and X3 labels read as metal and one LED reads as silk: a test that freed the labels turned more part ends into silk, so it was reverted. Silk on the bare bottom still takes a few copper-edge glints.

## The same code on the Driver board

Rerun from `copper prep` through `check fidelity` on a fresh copy of the loop 2 run, against that run's `copper.json` and `fidelity.json`. A rerun with the unchanged binary matched them exactly, so these differences are the code.

| Measure | Before | After | Change |
|---|---|---|---|
| Vias | 1329 | 1329 | 0 |
| Pours | 828 | 834 | +0.72% |
| Tracks | 2588 | 2546 | -1.62% |
| F.Cu held-out IoU | 0.823 | 0.825 | +0.24% |
| B.Cu held-out IoU | 0.873 | 0.873 | 0 |
| Silk, metal, mask and holes, both faces, held-out IoU | | | 0 |

All of the track change is on F.Cu (1754 to 1712; B.Cu is unchanged at 834). Pale neutral things wider than 1.2 mm are now opaque on a face with parts, so copper no longer runs through them: 53 of the 96 tracks that went and 43 of the 54 that came touch one of those bodies. Everything else takes its Driver value: the mask tone factors are 1, the light spread is over the line on both faces, the sharpening test finds none, and 684 top pits are rejected because 3 line up with the bottom against 9 by chance.

## A second board: Raspberry Pi Compute Module 5, from public photos

Run on the everypin pair only, 24 px/mm, framed through the four mounting holes (55 x 40 mm, 48 x 33 mm spacing, from the datasheet). No schematic, layout or test-point table was read, and nothing has been checked against one. See `method.md` for what changed and why.

| Stage | What it produced | Believable? |
|---|---|---|
| prep | every hole found once gold-only, flip undecided by holes | Yes |
| scale | 23.93 x 23.64 px/mm top, bottom on top at 0.021 mm RMS (0.046 leaving each of 21 tiles out) | Yes, by eye: outline and holes land on the frame |
| parts detect | 135 candidates, 58 match a size | By eye: ICs, the lid, the can, inductors and connectors are found. Many candidates are print, and most small passives are missed |
| copper prep, domes | 358 top and 755 bottom pits, 232 on both faces | Yes for pits in plain mask, see below |
| copper regions | 100 and 142 regions | Evidence only. The older region reader was not tuned for this photo |
| copper trace | 684 pours, 1254 tracks, 1229 mm, 767 vias; 3814 of 4759 islands not kept, mostly crumbs | Pours and their gaps yes. Tracks on clear mask yes, but in pieces: only 13 percent are over 2 mm, holding 687 mm of it. Under large print, and near parts, mostly no |
| layers trace | 204 and 427 silk polygons, 4 holes, 368 pads shaped | Silk and holes yes. Pads less so |
| build | 648 pads, 684 zones, 2 layers, bottom parts flipped | Written; only 58 parts, unnamed |
| check copper | passes with `--skip-earlier`, 1 inner via | Shapes valid. The one inner via proves nothing about layer count |
| check fidelity | below 0.8 on copper, metal and mask | See below |

| Layer | IoU, held-out tiles | Boundary median / p95, mm | Excluded mm2 of 2200 |
|---|---|---|---|
| F.Cu | 0.718 | 0.067 / 0.93 | 1355 |
| B.Cu | 0.763 | 0.033 / 0.90 | 956 |
| F.SilkS | 0.985 | 0 / 0.025 | 834 |
| B.SilkS | 0.983 | 0 / 0.025 | 286 |
| F exposed metal | 0.686 | 0.083 / 10.7 | 815 |
| B exposed metal | 0.673 | 0.025 / 2.2 | 267 |
| F.Mask opening | 0.711 | 0.20 / 10.8 | 815 |
| B.Mask opening | 0.690 | 0.025 / 2.2 | 267 |
| F holes | 0.821 | 0.025 / 9.8 | 895 |
| B holes | 0.904 | 0.025 / 8.95 | 329 |

**Those copper figures are the weakest kind.** The scorer's split comes from the same two green modes as the reader's, so it cannot show a wrong level, and it blurs the thinnest tracks away, scoring them as drawn but not seen. There is no second photo of this unit. Silk is self-agreement as on the Driver. The one independent check is the other photo set, read by the same program: everypin against CNX on held-out tiles gives 0.49 on F.Cu and 0.50 on B.Cu, and most of that gap is CNX, which reads badly (below). It neither confirms nor refutes the 0.72 and 0.76.

**Vias, held out.** Bars were set on tile set A. On tile set B, 128 of 191 top pits have a bottom pit within 0.1 mm, against 0 and 0 with the bottom mirrored either way. By eye on 6 tiles drawn after the method was frozen: 34 of 39 marked are real (0.87, Wilson lower 95 percent 0.73), and 34 of 37 real ones are marked (0.92, lower 0.79). The 5 false ones lie beside print, a part's end or a test pad's rim. An earlier draw of 6 tiles, 32 of 42, is what led to the pale-ring bar, so it is not counted. Pit widths form one population, 0.14 to 0.20 mm. Of 17 spots under 0.11 mm none lies on both faces, so if there are microvias these photos do not show them. A via with a part or heavy print round it is not read, and one under a part cannot be seen on that face.

**What these photos cannot give.** Connectivity, at the SoC, the BGAs and the fine-pitch fan-outs. No named net, no layer count. Inner layers are never seen, and the SoC's lid hides its whole neighbourhood.

**Smallest features at this resolution**, measured across lines on the original pixels. Everypin: thin tracks are 0.065 to 0.09 mm wide at half height, 1.6 to 2.1 photo pixels, which is the blur and not the track, so their width cannot be read. They stand 30 to 49 grey levels above laminate on a grain of 2.4. Parallel lines read reliably down to a 0.25 mm pitch (height 20 to 34), and at 0.15 to 0.2 mm (height 15 to 17) they read in places. Under 0.15 mm the height is grain (10). A gap between pours reads at 0.185 mm, 4.4 pixels, 17 percent deep. Print edges are 1.2 pixels wide. CNX at 31 px/mm: edges 3.1 pixels (0.10 mm), tracks 0.10 to 0.13 mm at half height and only 6 to 11 grey levels high, and lines thin out under a 0.2 mm pitch. CNX reads F.Cu 0.41 and B.Cu 0.33, and a 0.25 mm shift does not lower B.Cu, so copper on that set is a failure, left as it is.

**What it would take.** The Driver reads well with tracks and gaps at 5 to 9 pixels. For features of about 0.09 mm that is 55 to 100 px/mm with real optical resolution: an estimate from these two boards, not a test. 100 px/mm is 5500 pixels across this board. No sharpening: it digs false gaps.

## A third board: parts on board 10, and the same reader on the Driver and the CM5

Board 10 is a small green USB hub board, 38 x 39 mm, photographed at 76.8 px/mm. Its top face was labelled by eye from 3x tiles with a 0.5 mm grid: 97 parts, 67 of them chip parts. The left half (57 parts) was used to build the method, the right half (40 parts, 27 chips) was labelled after the method was frozen and scored once. A candidate locates a part when its centre lies within the larger of 0.45 mm and 0.3 of the part's short side. Sizes were read from 10x crops by the chip's own width: every "0805" of the first run on this board is an 0603 with wide fillets.

| Right half of board 10 (held out) | Before | After, all candidates | After, rated 0.5 or more |
|---|---|---|---|
| Candidates | 138 | 142 | 48 |
| Candidates that locate a real part | 45 (33%) | 47 (33%) | 30 (63%) |
| Real parts with a candidate, of 40 | 29 (73%) | 32 (80%) | 23 (58%) |
| Chips located, of 27 | 18 | 21 | 15 |
| Chips located with the right size | 2 | 7 | 7 |

Only the capacitors are sized. None of the 14 resistors on that half is read body first; they are located by fragments of the older detector.

`parts snap` on the same half, 26 capacitors and resistors given at the labelled place: given their true size, 20 kept it before (6 shrunk) and 26 now; given one size too large, 23 came out right before and 23 now; given one size too small, 8 before and 9 now.

| Chip passives read body first | Before | After |
|---|---|---|
| Driver top, 90 chips in the run's parts list | 19 found, 15 on a chip | 51 found, 41 on a chip, 34 at the list's size. By eye on the contact sheet about 9 are invented, 7 of them rated under 0.5 |
| Driver, all candidates | 668, 45 chips located, 20 right size | 640, 56 located, 37 right size. Resistors: 4 of 32 both times |
| CM5 top, 24 chips | 29 found, 24 located, 22 at the list's size | 36 found, 24 located, 15 at the list's size |
| CM5 bottom, 193 chips | 195 found, 193 located, 145 at the list's size | 203 found, 193 located, 145 at the list's size |

The CM5's parts list was built from the old reader's output, so its "before" is 100 percent by construction, and a different size on the top face is a disagreement with that list, not a measured error. Rerunning `parts snap` from the CM5 run's pre-snap state ends 212 of 217 chips at the run's final size (142 with the old rule), and 32 of 40 audited-ok placements unchanged (27); on the Driver 80 of 85 (79) and 23 of 37 (23).

A region of board 4 (five MOSFET channels, stitched close-ups, resampled to about 40 px/mm by eye) shows no capacitor and about 20 dark resistors: nothing is read body first there, the levels fall back to the scaled numbers, and the resistors are found only as unsized dark bodies.

## The flow's shape since 0.5.0

Routing is optional, there are two scores, `auto` runs the program's steps, and a bench passback exists (docs/method.md: "Hidden connections are left unrouted", "Two scores", "The bench passback", "`auto` and `next`").

Tested on copies of two finished runs, not on a new board end to end:

- **CM5 copy.** From `connect measure` through `report` without routing: `auto` took 69 seconds from the snapshot to the report and stopped once, for report.md. Attribution run again gave a byte-identical copper.json, so every audit stayed valid. Before: overall 0.0. After: photo score 0.0 (blocks 0.0 and identity 4.6, because that run tagged every block INFERRED and read 12 of 258 identities), bench score 0.0 (none of 217 unmarked values measured). By category the photo figures are 4.6, 16.2, 0.0, 54.2, 39.1, 40.0 and 37.5; connectivity as a whole went from 0.0 to 18.6 and layers from 28.8 to 30.0. 57 hidden connections are listed; the count of 10 layers stays as stated by its maker and the photos alone infer at least 4.
- **Driver copy** (made with an older version). Before: overall 0.0. After `layers state`: photo score 40.0, held by three audits that are stale or were never drawn; bench score 0.0, because without routing the layer count is UNKNOWN.
- **Tracing the copper again** on the CM5 copy does not reproduce the audited copper (857 vias against 883), so a pass from `copper trace` needs new independent audits; `auto` drew them and stopped for the verdicts.

Not done or still wrong:

- No board has been run from `init` with `auto`. The stops for the scale, parts.json and blocks.json are covered by unit tests of the plan only.
- KiCad shows more ratsnest lines than `unrouted.json` lists: 499 on the CM5 copy against 57. KiCad counts every piece of a net's copper that the drawn shapes do not join, and all 499 are pieces of GND that meet on inner planes. The list counts groups of pins. Nothing reconciles the two yet.
- The bench plan picks pads by a fixed order of preference, not by anything measured about access, and was never tried on a real board. Its made-up results file was ingested on a scratch copy only.
- A bench value is taken as typed: the program cannot tell an in-circuit reading from a true one.
- The photo score on a run with thin AI inputs is still 0.

## A run that finishes when a reader fails (2026-11-11)

Seven boards went through `auto` on 2026-11-10 and four stopped for good at `check copper`, with no review, tests, report, bench plan or video. The check was right each time, and nothing a runner may type changes a reader's result. The flow now carries such a failure instead of stopping on it (`src/notread.rs`):

- A face whose copper cannot be read is NOT READ. The reader says so itself at trace time where it can (`faceread`: the face's islands are taken out, `detect/copper-island-accounting.json` carries `unread` with why); what only `check copper` finds (one island with most of a large part's pins) is recorded by the check. Both end in the same record, `checks/copper.ok` `summary.notRead`, and the check answers that it recorded a failure, not that it passed.
- A face no photo shows is NOT PHOTOGRAPHED: `connect measure` and `connect attribute` work on the face that exists.
- What follows is the same for all three: attribution takes no join from that face, so no net is claimed through it; the copper and connectivity scores carry a ceiling "faces whose copper was read" (one of two faces: 50) and no audit sample is drawn on that face; the review lists a finding; `tests generate` writes `T-copper-not-read-<side>`; `report` refuses a report.md without the sentence; the net pictures leave that copper out and print a band over the face; the schematic's root sheet and the video say it; every stop of `auto` repeats it under "Carried as failed, not waiting for you".
- Proven on a copy of test board 1 (bottom: one island with 102 of 130 pins): `auto` went from `check copper` through build, the mimic check, the snapshot, nets, layers and the schematic check to the first review pass and stopped at "AUTO NEEDS AI: independent audit verdicts".

Not done: with one face only, `layers trace`, `check fidelity` and the copper audit still need both board images, so they are skipped or capped and say so; the KiCad copy still holds whatever the reader drew on a face the check failed.

Two more stops of the same family, handled the same way:

- `check mimic` "zones with no fill". The program fills read pours itself, and exposed metal no footprint explains (PHOTO1.M) was subtracted as the box round its outline: on test board 4 that box wiped an 8 mm2 island whole. A read pour is no longer cut by it. A pour that other pads still cover whole (board 6: two islands of 4 and 5 mm2 inside one pad and its clearance) is recorded by `build` in `build-left-out.json` (`noFill`, with area and what covers it); `check mimic` passes and lists it as a finding, and the review lists it. `build` also keeps one fill mask per layer, not one per pour: 1201 pours on board 11 had taken 6 GB.
- `check schematic` ERC errors. An error of type pin_to_pin or pin_not_driven whose pins the copper as read joined on one net is a finding (`src/ercfind.rs`: pins, net, copper pieces, a continuity test `T-erc-<pins>`), carried by a connectivity ceiling "nets the electrical rules accept". Any other ERC error, and one on a net somebody stated, still fails. Board 6: 7 such errors on 5 of 29 nets, ceiling 82.7.

Proven by runs on copies, each to "AUTO NEEDS AI: independent audit verdicts": board 1 (bottom NOT READ), board 4, board 6, board 11 (one face, the other NOT PHOTOGRAPHED).

Other faults of the unprompted sequence fixed the same day: `parts snap` runs once after the AI completes parts.json even when `check parts` was run by hand; the joins of pads to copper are read again when a part moves, turns or changes footprint; `review pass` waits for earlier steps as every check does; a restitch (`stitch --top`) sends the plan back to `prep`; `build` names a part whose footprint did not load (`build-left-out.json`) and a new footprint file under `reverse-flow/lib/fp/` makes the build run again; a position with no part fitted is not asked for datasheet pins; keep-out rule areas are not "zones with no fill"; an auditor may correct their own verdict, with a note, while the sample is not complete; a size is stated as the photographed window's when a side of the outline is the photo's edge (`src/window.rs`); and `auto` gives a reason when a step was killed or died on an allocation.

## The datasheet witness (2026-11-10)

`datasheets/<ref>.pins.json`, the stop in `auto`, pin names into the schematic and onto proven copper, and `connect witness` are described in `method.md`, "Datasheet pins". What it gave on the two runs it was tried on:

| Run | Chip, pins | Pins with a solid contact | Agree | Disagree | Not visible | Nets with a witness | Against the net list |
|---|---|---|---|---|---|---|---|
| Driver (built on this run) | U2 DRV8323S, 41 | 4 | 0 | 1 | 40 | 1 of 77 (35 carry a datasheet pin) | 21 agree, 2 disagree, 18 not stated |
| Driver, nets.json removed, so nets from copper alone | U2, 41 | 4 | 0 | 0 | 41 | 0 of 18; 4 nets took their name from a U2 pin | 0, 0, 41 |
| Board 10 pilot (held out) | U1 USB2532, 37 | 0 | 0 | 0 | 37 | 0 of 3 | 0, 0, 37 |

- **It is only as good as the copper at the chip's pads.** At 0.5 mm pitch the reader joins the tracks leaving a QFN into one piece, attribution leaves those pads unsettled, and the witness has nothing to stand on. It says so with a picture (`unresolved-<ref>.jpg`): 34 of the USB2532's pins on one piece on board 10.
- **The STM32G4 on the Driver has no witness.** Its marking was not read (the family is from silkscreen), so no pins file is accepted for it.
- **The three Driver findings were looked at in the pictures, not settled.** The exposed pad's pour joined to pins the net list calls VIN: either the 17 vias, the bottom pour or the typed net names are wrong, and the photo does not say which. CPL and CPH: the capacitor the net list took for the flying capacitor (C37) sits 7 mm away on a pour, and two capacitors sit beside the pins, so the typed net is the likelier error.
- **`expects` checks parts, not values.** A 47 nF capacitor and a 10 uF one are the same to it.

## The run video

`video build` makes the two minute video described in the README, and `auto` runs it after the report. Tried on copies of two finished runs and on scratch runs that stop after the photos, not on a board run from `init` to the end:

| Run | Video | Scenes | Voice | Build |
|---|---|---|---|---|
| CM5 copy, through `auto` | 123.8 s, 1920x1080 at 30 fps, H.264 and AAC, 44.5 MB | 12 of 12 | adom-tts, 21 lines spoken, 19 left out for time | 70 s |
| Driver copy (older run: no `nets/` folder, no schematic pictures, two steps not done) | 123.8 s, 44.9 MB | 11 of 12: no schematic scene; the nets scene coloured the copper by rung itself; the end card says which steps are not done | adom-tts, 21 lines spoken, 11 left out | 81 s |
| Scratch run made by `init` alone on a stitched photo pair | 118 s | 4 of 12 (title, photos with the join maps, scores, end) | none: built with captions only, with adom-tts pointed at a missing program | 74 s |
| Scratch run of board 4 after `init --photos` and `stitch` | 118 s | 4 of 12, the photo scene with all ten photos and both join maps | none (`--no-voice`) | about 80 s |

What was checked: `ffprobe` on each file, one frame from the middle of every shot of both copies read by eye, the captions, and `video.json` against the files. `auto` with the Python interpreter pointed at a missing program ended `AUTO COMPLETE: every step is done; the video was NOT built: ...` with exit 0, `steps` showed `fail  video`, and a second `auto` did not try again.

Not done or still wrong:

- Nobody has watched the videos play. The frames, timings and sound files were checked; the motion and the voice against the picture were not.
- The voice fits about 25 short lines in two minutes. On the CM5 copy 19 template lines were left out for time, among them the scale's source and the bench plan; they are on the panels and in `video.json`.
- KiCad's own picture of the copy is lined up with the photo by the board's outline (the rows and columns that are at least 60 percent solid). That holds for a rectangular board, also with a connector hanging over an edge (the Driver). A board that is not a rectangle fails the proportion check and the scene falls back to the program's overlay.
- The board panel of `nets/confidence-<face>.jpg` is cut out by the layout `nets draw` uses today (margins of 12 and 108 units). The tool checks the picture's size against that layout and draws the copper by rung itself when it does not match, so a change there costs the program's own picture, not the scene.
- The photo scene for a run started with `init --photos` (the photos as they came, then the join maps) was tried on board 4 after `init --photos` and `stitch` only: ten photos shown, both faces with their source maps, 0.41 and 0.39 pixels of overlap disagreement read from `stitch.json`. No run that was started that way has reached the report yet, so the full video on such a run is untried.
- A scene's wording is fixed English templates. The only free text is `video-notes.json`, which is spoken as written and not checked against the run.
- The fonts are the system's DejaVu Sans when present, else Pillow's built-in font; the look with the built-in font was not checked.

## Known gaps

- **Schematic: nets between two ICs or connectors of one block go by label.** A strip runs from a pin to its passives; it does not run to another IC or connector. Transistors that share a node are wired as a column (a half-bridge reads as one), but three connectors on one bus each carry the bus names, and an IC and the header beside it meet by label. `check schematic` counts these as label hops (a warning).
- **Schematic: no notes on the sheet.** The owner's rules ask for the reason for each value beside the part. The run holds a `function` and a `why` for most parts and nets; they are in the Description field, not drawn.
- **Schematic: a block sheet may be mostly empty.** One sheet per block, and a block that is a little too tall for A4 takes a whole A3.
- **Nets by confidence (`nets draw`).** On the Driver run all 77 nets are `inferred` by their weakest link, though 74 percent of the copper area is on the `copper` rung: 336 of 415 pins have no solid contact to their net's copper. On the CM5 run 52 of 192 nets are `copper` (21 of two or more pins, 31 of one pin) and 140 `inferred`. No net is `via` on either run: where verified vias join two conductors of a net, some pin of that net is still unseen. The levels are only as good as attribution, and a level says nothing about whether the name is right. The page nets/view.html was checked by running its script against stubs of the browser, not in a browser.

- **No stackup closes every connection at default rules.**
- **Vias as holes (2026-11-10, `viasig.rs`).** On the USB hub (board 10) the readers kept no via; now 127 on the top and 152 on the bottom, each with its reason in `detect/via-spots.json`. Held-out by eye on 8 tiles: precision 42 of 44 (0.95, Wilson 0.85 to 0.99), recall 42 of 45 (0.93, 0.82 to 0.98). `scale` now lays the bottom on the top through 104 vias both faces show (leave-one-out 0.025 mm RMS; the hole fit left 0.30 mm). CM5: 1155 kept before, 946 now; of the audited places, 39 of 43 real vias still kept, 14 of 14 wrong ones dropped. Driver unchanged. Still wrong: vias whose hole the mask has closed are not read (ring or glint only: all of the red and the blue test boards, and single vias on board 10); a spot kept on one face alone with no ring is weak evidence among parts (CM5: roughly a third of the newly kept ones looked false); cross-face pairing assumes through vias, so on a board with blind vias a real via on a bare face with nothing on the other is dropped unless it has a ring; all sizes at 40 px/mm.
- **Some false vias remain, and faint specks are unresolved.** About 3 percent of kept vias are false: mainly rims of soldered pins and track edges read as rings. Tiny faint specks are kept or dropped inconsistently and could not be told apart by eye. Counting every kept one as false lowers held-out precision to 0.87.
- **No inner vias.** The photos prove no minimum layer count, so routing now starts from 2 layers. The figures in the layer table below predate the new vias.
- **Scale has one source.** The body check only picks the pitch standard (41 px/mm against 46.6), so the number rests on the hole rows alone.
- **The published snapshot is out of date.** It predates the final copper. The flow now shows a snapshot stale when copper changes; the published run has not been re-snapshotted.
- **Pad connections on the top face are still weak.** The bottom photo shows plated pins' rings well. Fine-pitch pins on the top, whose pads the body hides, settle little.
- **Vias on a boundary.** 98 vias sit where two conductors are both reachable. They join neither and are listed in `viasOnBoundary`.
- **Attribution still rests on inferred pin names for most pins.** Connections the copper does not support are in `unsupported` in net-evidence.json. 129 are listed, nearly all pads with a gap closed around them and no track seen leaving, which does not rule out a track hidden under the part.
- **Most via sizes are not the pad's.** Only rings (about 180) measure the pad. Blobs and edge domes record the visible dome, about 0.23 mm, and arcs take the rings' median. All drills are assumed. Kept domes show on the bottom only, so a via hidden on that face is missed.
- **Copper against the photos, held-out eye labels.** Coverage bottom 90%, top 87%; false coverage bottom 15%, top 12%. Edge distance, photo edge to drawn edge, median 0.05 mm on both faces, 95th percentile 0.6 to 0.8 mm. Drawn edge to photo edge is worse, because grain and dome shadows still draw edges the photo does not have.

- **A via on the boundary of two pours can attach to the wrong one.** Read on the Driver photos at v276 and v289: two real domes tie a 34 mm2 field group to GND through a tip of the wrong piece, so its `via` rung name is suspect.
- **Attribution rests on inferred pin names.** See `connect attribute` and net-evidence.json for what each net's copper actually shows. Several two-pin parts look swapped.
- **Via pads rest on a tenth of the vias.** 120 vias on laminate show their pad, median 0.508 mm, 10th to 90th percentile 0.444 to 0.688, so every via is written at 0.50 mm. Vias in pours are assumed to be the same. All drills are assumed. Kept domes show on the bottom only, so a via hidden on that face is missed.
- **Edges.** Drawn edge to photo edge, median and 95th percentile: bottom 0.19 and 2.19 mm (0.38 and 2.45 before), top 0.68 and 4.75 mm (unchanged). Photo edge to drawn edge: bottom 0.075 and 1.02 mm (0.055 and 0.82 before, partly because dome edges are no longer drawn), top 0.055 and 0.71 mm (0.05 and 0.75 before). Drawn edges sit 0.025 mm inside the steepest fall of brightness at the median.
- **Vias named against their pour.** About 130 vias per face sit in a pour of another net with no gap on the photo. Most are naming errors. Each keeps a 0.05 mm ring so it does not short.
- **Over-splitting.** The reader leans towards splitting, so pours in dome fields and tracks in grain are often several items. Each still gets its own net later; none of the splits is a short.
- **Copper around top-face parts is the weakest reading.** Tall parts cast shadows that neither reader can see through, and two neighbouring pads can read as joined. Small holes on the top grew from 10.5 to 15.3 mm2 in the held-out tiles.

- **False vias.** Up to 338 of the 1028 kept vias land on pale pixels (a 0.35 mm patch more than a quarter pale), mostly silkscreen letters and lines. They feed net assignment and block the router. The via filter does not reject silkscreen yet.
- **Inner vias are not proof.** The 3 read as leading only inward look like ordinary domes in a stitching field, so the photos prove no minimum layer count.
- **The saved snapshot is out of date.** The last one predates the final copper.
- **Bottom's upper-left rails are largely missing** from the copy. The photo is darker there and the islands fragment.
- **Signal bundles on the bottom** come out mostly as gaps in the pour, not separate tracks. Tracks of unknown net shorter than 0.8 mm are dropped, 637 fragments in all.
- **Pad connections are weak evidence.** The ring test does not reliably tell a joined plated pad from an isolated one on these photos. 99 pins disagree with the copper they appear to touch, and 4 net pairs meet at vias.
- **827 mm² of pour and 94 mm of track have no net.**
- **Routed copper is one way to make the connections**, not what is inside the board. Inner layers are never seen.
- **Tracks do not yet claim copper of unknown net.** The router pays to cross it where it could be following it.
- **KiCad refilling zones is untested.** Outlines now carry a pour's holes, but the service cannot refill. DRC counts barely change between the measured zone clearance and the rule's (510 against 506 clearance errors), which suggests the net class's 0.2 mm still applies, so a refill would probably cut narrow gaps back.
- **Tested on two boards, read well on one.** Most thresholds came from the Driver photos; the CM5 section above says what moved and what is left.

## Before making it public

Done in 0.5.0: eleven more boards were run and seven of them graded against their real designs (last section). No X-ray was used. The rules question above is still open.

## Photo intake on the eleven test boards (2026-11-10)

`init --photos` and `stitch` were run on every photo of each test board with no labels. The figures are from `stitch.json` of each run; the mosaics, reports and evidence pictures are in `RE_Flow_Test/mosaics/board<NN>/`. The method was developed on these same boards, so the figures are not a held-out test of the method. What is held out is within each face: the overlap figures in the last column are on cells the placement was not fitted on. The joins of boards 1 to 8 were looked at as full-size crops (`<face>-seams.jpg`, twelve per face) on 12 of the 16 faces; not looked at in their final form: board 2 top, board 3 bottom, board 6 bottom, board 7 bottom.

| Board | Face | Tiles | Close-ups % | Overview fill % | Cells | Median px | 95th px | Held-out median / 95th px | `prep` outline |
|---|---|---|---|---|---|---|---|---|---|
| 1 | top | 3 | 87.4 | 12.6 | 45 | 0.37 | 2.38 | 0.34 / 2.39 | found |
| 1 | bottom | 3 | 85.2 | 14.8 | 10 | 1.60 | 13.67 | 1.12 / 1.64 | found |
| 2 | top | 5 | 82.3 | 17.8 | 543 | 0.49 | 2.93 | 0.47 / 3.10 | found |
| 2 | bottom | 4 | 76.4 | 23.6 | 49 | 0.42 | 1.98 | 0.44 / 1.16 | found |
| 3 | top | 4 | 97.2 | 2.8 | 60 | 1.36 | 7.09 | 1.31 / 7.22 | found, but it stops at the metal connectors |
| 3 | bottom | 4 | 98.8 | 1.3 | 657 | 0.43 | 1.23 | 0.43 / 1.22 | found |
| 4 | top | 4 | 97.6 | 2.4 | 285 | 0.41 | 3.69 | 0.42 / 3.65 | found |
| 4 | bottom | 4 | 92.0 | 8.0 | 577 | 0.40 | 2.65 | 0.38 / 2.69 | found |
| 5 | top | 4 | 93.9 | 6.1 | 356 | 0.46 | 1.76 | 0.52 / 2.02 | found, but it stops at the row of terminal blocks |
| 5 | bottom | 4 | 94.4 | 5.6 | 139 | 0.40 | 0.97 | 0.40 / 0.91 | found |
| 6 | top | 4 | 92.7 | 7.3 | 898 | 0.34 | 0.89 | 0.34 / 0.93 | found |
| 6 | bottom | 4 | 99.4 | 0.6 | 458 | 0.39 | 0.95 | 0.40 / 0.94 | found |
| 7 (red) | top | 4 | 92.0 | 8.0 | 88 | 0.38 | 2.89 | 0.38 / 1.28 | not by `prep`'s green test; taken from `stitch.json` |
| 7 (red) | bottom | 4 | 90.5 | 9.5 | 68 | 0.38 | 1.04 | 0.32 / 1.05 | not by `prep`'s green test; taken from `stitch.json` |
| 8 (blue) | top | 4 | 92.5 | 7.5 | 203 | 0.40 | 1.24 | 0.38 / 1.11 | not by `prep`'s green test; taken from `stitch.json` |
| 8 (blue) | bottom | 4 | 92.0 | 8.1 | 19 | 0.55 | 5.69 | 0.55 / 6.35 | not by `prep`'s green test; taken from `stitch.json` |
| 9 | top, bottom | 1 each | 100 of what the photo shows | 0 | 0 | none | none | none | found; the board runs out of both photos left and right |
| 10 | top, bottom | 1 each | 100 | 0 | 0 | none | none | none | found |
| 11 | top only | 3 phone photos | 99.6 | 0 | 70 | 1.38 | 4.62 | 1.58 / 9.10 | found |

Pixels per mm are not settled here. `prep` lists candidates near 52 to 53 px/mm on boards 1, 2 and 4, where 0.4 px is about 0.008 mm; `scale` decides.

**What the figures do and do not show.**

- Nothing is "not seen" inside the board outline on boards 1 to 8. The overview fill, 1 to 24 percent of a face, is real board at a quarter to a sixth of the tiles' resolution, and a track crossing from a tile into it can step sideways by the overview fit (8 to 20 px on these boards). Board 2 has the most: its close-ups leave the middle of both faces uncovered.
- Three faces rest on few cells: board 1 bottom (10), board 8 bottom (19) and board 2 bottom (49). Those faces are bare mask with little a feature can hold: no pair of tiles could be linked on board 8's bottom, and two of three on board 1's bottom, so the overview placed those tiles and surface cells in the overlaps then refined them. Their joins are good to a few pixels, not to the half pixel of the others.
- Board 3's top reads 1.4 px at the median on 60 cells: tall parts leave little board surface in the overlaps. The joins looked at are clean.
- Board 11 has no overview and five hand-held phone photos. Three overlap and make the top; the other two match nothing and are listed as unplaced, since the photos cannot say whether they are another part of the top or the other face. The tiles are placed by similarities although a hand-held phone gives perspective; the 1.4 px is what that costs.
- Boards 9 and 10 have one close-up per face and nothing to stitch. That the two photos are the two faces is an assumption, and `stitch.json` says so (`facesAssumed`).

**What the crops show that the figures do not.**

- Between two tiles, tracks, pads and print run across the joins without a step on every face looked at.
- Board 4 bottom has grainy, brighter bands 50 to 150 px wide along three joins on bare mask (`bottom-seams.jpg`, crops 5, 7 and 12). The geometry agrees there and the tone does not: a thin strip of one tile's edge lies inside another's area and the join gain did not bring it level. A copper reader could take such a band for the edge of a pour. Not fixed.
- Where the overview fills in, the patch is plainly softer and its tone is off (darker on boards 4 and 8, pinker on board 7, greyer on boards 2 and 5), with a hard edge against the tiles. On board 6 top a part at such an edge shows twice, a few pixels apart.
- Board 1 bottom and board 5 bottom keep a visible step in tone at one join each.

**The top.** Clear and right on boards 1, 3, 4, 5, 8, 9 and 10. Close and right on board 7. Close on board 6, where both faces are populated. Close and wrong on board 2: its bottom carries many small parts and scores 0.049 against the top's 0.043. The delivered board 2 was stitched again with `stitch --top Board2.11.jpeg` after looking at both mosaics; `stitch-automatic-top.json` next to it is the automatic report.

**Known gaps.**

- `prep` assumes a green mask. On the red and blue boards it takes the board box from `stitch.json` and says so; that box includes connectors that hang over the edge (board 8 top: 93.0 mm against 86.0 mm on the bottom), so the faces lie 1 to 2 mm off each other. Copper is read through a red or blue mask (`maskread.rs`, docs/method.md): good on the red bottom and the blue bottom, weak on the blue top, and fine tracks on the red top are not separated. Tented vias are not read: no via is kept on boards 7 and 8. Holes and bodies in `prep` and `detect` still use green thresholds.
- `prep`'s own outline stops where parts cover the board edge (board 3 top, board 5 top). `stitch.json` has a board box cut from the overview for each face (`boardBoxPx`), which includes parts hanging over the edge; nothing uses it on green boards yet.
- The overview is mapped by one homography. A fill region is therefore out by the overview fit at its border with the tiles.
- A face with no overview and tiles that do not overlap cannot be assembled: each group stays separate.
- The registration needs Python with OpenCV on the machine. The binary reports a clear error when it is missing.
- OpenCV 5.0.0's `phaseCorrelate` changes its inputs in place. The earlier one-board stitcher (`CM5_RE/tools/stitch.py`) cuts overlapping cells from one array, so its overlap figures were read from data already windowed and are too good; they should be measured again before they are quoted.

## Laying the faces on each other, the outline, and `reframe` (2026-11-11)

**What changed.** `prep` no longer assumes that the outlines of the two photos coincide (`src/facereg.rs`, `src/outline.rs`).

- The board mask is the photo's own: within 30 degrees of its hue peak, above 0.8 of the 2nd percentile of its own value, and only where 60 percent of the pixels round a pixel pass. The grain of a shadow under a board's edge and of a blue table no longer counts as board.
- Round pads, rings, test points and solder joints are found on the whole photo of each face. Both ways of turning the board over are tried, and the bottom-to-top map is the similarity most point pairs agree on, then an affine fit, then a homography, in photo pixels. No outline enters it. Six matches with two outline edges agreeing, or twelve, register the faces. Below that the large openings are tried, then the outlines themselves (an edge with solder mask beyond it is not used); the last is reported as WEAK and cannot say the flip.
- Both faces get one outline: the two masks are laid together through the fit and the outline is fitted to their union, because parts over an edge hide the board on one face only. Both photos are straightened through it. Sides that run along the photo's own edge are recorded as `notBoardEdge`.
- `scale` lays the bottom through that fit (the bottom photo's corners become where the top's lie in it) and records `alignment.faces`. `check prep` fails when neither holes nor vias hold the faces, unless the flip was stated, and then it warns.

**Measured on copies of the test runs** (matched points, residual of those points after the fit, and how far the same points lay apart with each face on its own outline):

| Board | Flip | Matched (other way) | Residual mm RMS / worst | On own outlines mm RMS / worst | Outline mm (before) |
|---|---|---|---|---|---|
| 4, stitched | y, found | 28 (8) | 0.137 / 0.195 | 0.243 / 0.400 | 101.92 x 69.46 (top 101.66 x 70.39, bottom box 2.3 mm too tall) |
| 5, stitched | not found; y stated | 0: through the outlines | none | none | 102.71 x 70.35 (102.56 x 53.07) |
| 9, cut left and right | x, found | 73 (24) | 0.027 / 0.098 | 2.023 / 4.474 | 44.16 x 26.14, left and right not the board's edge |
| 10, single photos | x, found | 37 (15) | 0.060 / 0.142 | 0.104 / 0.212 | 37.95 x 37.89 (38.12 x 39.04) |

Board 10's via relay then pairs 128 vias (104 before) at the same 0.025 mm on pairs left out of its fit.

**`reframe`** moves a run made before this onto the new frame without typing anything again: the scale, the flip, every part of parts.json, the candidate ids and the dismissals are carried through the photo each was read on, and what was derived from the old frame is set aside for `auto` to make again. `reframe --flip x|y` states the flip when the old run never settled it and the photos cannot say.

**Known gaps.**

- Thresholds in `facereg.rs` and `outline.rs` are in photo pixels read at 65 to 77 px/mm (the 2026-11-10 close-up sets), and say so where they are defined. A photo at a very different scale needs them scaled.
- A square board photographed with one face turned a quarter turn is not tried: only the two flips are.
- On board 5 nothing that goes through the board is found on both faces (its mounting holes touch the board's edge and the pads test wants a pad ringed by mask), so it rests on the outlines and a stated flip.
- The old rulers' end points were not recorded, so `reframe` carries the scale as the mean over the old straightened top and prints the range (0.5 percent on board 4, 1.9 percent on board 5, whose old picture was sheared). `scale` records the ends from now on.
- The via relay did not pair on board 4 after the new fit: it wants 40 via pairs for its quadratic and this board has about 21 vias in all. The faces there rest on the 28 matched pads; `copper prep` then reads 21 vias on the reframed copy where the run before read 7.
- Board 6 (both faces populated, terminal blocks over both long edges, a header over a third) is NOT registered and says so. Its pads test finds nothing shared but two mounting holes of one size; a third is read at half its size on the top, and two holes alone are accepted only when no other pair of openings fits another way, which is not the case here. The outlines disagree with the holes, so the outline fit is refused too (an earlier build claimed it, with a bottom-to-top scale of 1.04 and holes 1.5 to 3.6 mm apart). The run keeps its old frame, 98.65 x 61.44 mm, which takes the terminal blocks as board: their green is the mask's hue and value, and nothing here separates them.
- A fit through large openings must agree with the openings' own diameters within 8 percent, which ties its scale to something measured. A scale away from 1 is not refused by itself: the two mosaics of board 5 differ by 5 percent in pixels per mm and register rightly.

## The eleven test boards at the end of the build-and-test run (2026-11-11)

Every board went through `auto` to "AUTO COMPLETE" with its copy, schematic, net pictures, tests, report, bench plan and two minute video. No run reached the 90 percent target, and none is a usable copy of its board: the photo score is the lowest category, and connectivity, copper or blocks is near zero on every board. The runs are kept by the maintainer and are not part of this page: several of the boards are unpublished designs.

| Board | Real layers | Layers the run stated | Parts | Nets | Pads on a net | Vias read | Review | Graded against the real design (totals only) |
|---|---|---|---|---|---|---|---|---|
| 1 Control board, 160 x 45 mm | 4 | unknown, at least 2 | 83 | 51 | 124 | 0 | 0.0 STALLED | parts 66% found, 89% right, 0.24 mm; copper overlap 48% top, 54% bottom; pin pairs 23% right, 22% found; vias 0 of 134 |
| 2 Battery monitor evaluation board | not known | unknown, at least 4 (inferred) | 316 | 140 | 158 | 287 | 1.2 STOPPED | no board file found |
| 3 Raspberry Pi 5 | not published | unknown, at least 4 (inferred) | 98 | 34 | 65 | 577 | 0.0 STALLED | no public layout |
| 4 MOSFET driver board with a microcontroller module | 2 | unknown, at least 2 | 101 | 24 | 87 | 21 | 0.0 STOPPED | parts 95% found, 87% right, 0.23 mm; copper 36% top, 57% bottom; pin pairs 24% right, 13% found; vias 33% found, 90% right (the design file is one revision newer than the board) |
| 5 Automotive Ethernet switch | 4 | unknown, at least 2 | 242 | 177 | 317 | 0 | 0.0 STALLED | parts 96% found, 96% right, 0.27 mm; copper 16% top, 11% bottom; pin pairs 30% right, 4% found; vias 0 of 314 |
| 6 Sequent Microsystems 16 inputs HAT | not published | unknown, at least 2 | 354 | 130 | 309 | 0 | 0.0 STOPPED | no public layout found |
| 7 TI MSP-EXP430F5529LP (red mask) | 2 | unknown, at least 1 | 111 | 169 | 210 | 0 | 0.0 STALLED | TI's Eagle board through KiCad's import: parts 70% found, 78% right, 0.44 mm; copper 19% top, 3% bottom; pin pairs 39% right, 3% found; vias 0 of 444 |
| 8 Earth People Technology MAX V board (blue mask) | not published | unknown, at least 1 | 139 | 140 | 208 | 0 | 0.0 STALLED | no public layout found |
| 9 Battery charger board, two partial photos | 4 | unknown, at least 2 | 86 | 9 | 45 | 0 | 0.0 STALLED | placement list only: parts 67% found, 84% right, 0.12 mm |
| 10 USB 2.0 hub board | 4 | unknown, at least 2 | 97 | 10 | 22 | 154 | 4.1 STALLED | parts 75% found, 99% right, 0.08 mm; vias 90% found, 99% right; copper 29% top, 65% bottom; 20 of 279 pins on a net (119 with nets built from the pinouts, pin pairs 87% right, 7% found) |
| 11 Control board, one face, five partial photos | 6 | unknown, at least 1 | 158 | 238 | 350 | 0 | 0.6 STOPPED | parts 35% found, 67% right, 0.73 mm; copper 8% top; pin pairs 23% right, 1% found; vias 0 of 640 |

Layers: no run stated a layer count. Each stated a minimum from what the photos show, and no minimum was above the real count. Of the seven boards whose stackup is known (two of 2 layers, four of 4, one of 6), the minimum equals the real count on one, the 2-layer board 4. Inner layers leave nothing in a photo of either face unless a via ends inside the board, and no run saw one.

What the grading says: part positions are the strong result (0.08 to 0.44 mm on whole-board runs, and most parts found where the person running the flow read the board by eye). The nets are the weak one: at most a quarter of the real pin pairs are found, and of the pairs a run states, a quarter to two fifths are right, except on board 10 with nets built from the pinouts. Vias are read on green boards with open vias only. The layer count was never stated.

Changes made in the last hours, each from a board that could not finish:
- `check review` accepts a stop that carries its reason (`review pass --max-passes <n> --note "<why>"`), and `auto` keeps that stop when later steps change files. Before, a copper sample voided by a planted claim was drawn again, larger, without end (boards 3 and 4: five voided samples), and a scored sample was extended every time.
- An extension nobody judged no longer lifts an audited category to the unaudited cap: the judged part, being the first items of the same random order, is scored as the smaller sample it is (board 11: connectivity audited at 0.6 read 40).
- An ERC error among pins the copper joined inside a net built from the pinouts is a finding with a test, not a stop (board 6).

Open at the end:
- The copper audit cannot be judged on stitched photos: auditors who answer from the look of the mask accept planted claims, and an auditor who answers only what the crop settles returns "cannot tell" on 84 to 107 of 116 points. The crop needs the evidence that settles a point (edge map, both exposures, a wider view), or the category needs another measure.
- The part finder proposes few whole parts: on most boards the parts were entered by the person running the flow from the photos. The video still says "parts found".
- Copper is merged into large areas on stitched faces (one ground group of 145 pins on board 6), so nets from copper are few and many are wrong; mask-covered vias are not read; red and blue masks give no vias.
- The schematic is a pin list wherever the nets are weak: correct symbols and pin names, labels ending in "?", passives unconnected.
- Faces registered through the outline only on boards 5, 7 and 8, and not at all on board 6.
- The video's figures follow the files, but its wording overclaims in places ("joined by seen copper", "marking read" counts entries that say none).
- Native photo resolution is not built.
- `auto` on a run made by an older build rebuilds the pinout nets, which can stale its audit samples.