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AGRV2KL64

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AGM Microelectronics Programmable Logic Device (CPLDs/FPGAs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AGRV2KL64

AGM Microelectronics · Programmable Logic Device (CPLDs/FPGAs) · LQFP-64(10x10)

AGRV2KL64 from AGM Microelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD33 power_in 3.3 V supply pin, monitored by the power-on reset circuit.
2 IO_GB/PIN_2 bidirectional General-purpose 3.3 V LVCMOS/LVTTL I/O that doubles as a dedicated global clock input.
3 NC unconnected No connect.
4 NC unconnected No connect.
5 NC unconnected No connect.
6 NC unconnected No connect.
7 NRST input Reset pin.
8 IO_GB/PIN_8 bidirectional General-purpose 3.3 V LVCMOS/LVTTL I/O that doubles as a dedicated global clock input.
9 IO/PIN_9 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
10 IO/PIN_10 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
11 IO/PIN_11 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
12 GND power_in Ground.
13 VDDA33 power_in 3.3 V analog supply pin.
14 IO/PIN_14 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
15 IO/PIN_15 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
16 IO/PIN_16 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
17 IO/PIN_17 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
18 GND power_in Ground.
19 VDD33 power_in 3.3 V supply pin, monitored by the power-on reset circuit.
20 IO/PIN_20 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
21 IO/PIN_21 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
22 IO/PIN_22 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
23 IO/PIN_23 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
24 IO/PIN_24 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
25 IO/PIN_25 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
26 IO/PIN_26 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
27 IO/PIN_27 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
28 IO/PIN_28 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
29 IO/PIN_29 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
30 IO/PIN_30 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
31 IO/PIN_31 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
32 VDD33 power_in 3.3 V supply pin, monitored by the power-on reset circuit.
33 IO/PIN_33 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
34 IO/PIN_34 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
35 IO/PIN_35 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
36 IO/PIN_36 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
37 IO/PIN_37 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
38 IO/PIN_38 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
39 IO/PIN_39 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
40 IO/PIN_40 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
41 IO/PIN_41 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
42 IO/PIN_42 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
43 IO/PIN_43 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
44 IO/PIN_44 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
45 IO/PIN_45 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
46 TMS input JTAG test mode select input (IEEE 1149.1), 3.3 V I/O standard.
47 IO/PIN_47 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
48 VDD33 power_in 3.3 V supply pin, monitored by the power-on reset circuit.
49 TCK input JTAG test clock input (IEEE 1149.1), 3.3 V I/O standard.
50 IO/PIN_50 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
51 IO/PIN_51 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
52 IO/PIN_52 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
53 IO/PIN_53 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
54 IO/PIN_54 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
55 IO/PIN_55 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
56 IO/PIN_56 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
57 IO/PIN_57 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
58 IO/PIN_58 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
59 IO/PIN_59 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
60 GND power_in Ground.
61 IO/PIN_61 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
62 IO/PIN_62 bidirectional General-purpose 3.3 V LVCMOS/LVTTL user I/O.
63 GND power_in Ground.
64 VDD33 power_in 3.3 V supply pin, monitored by the power-on reset circuit.

Key specifications

Parameter Value
Manufacturer AGM Microelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating junction temperature -40 85 ℃ 2
SLICE Combinatorial LUT Delay TLUT 1.111 ns 9
SLICE Register Clear Delay TCLR 0.032 ns 9
SLICE Register Preset Delay TPRE 0.408 ns 9
SLICE Register Setup TSU 0.664 ns 9
SLICE Register Hold TH -0.636 ns 9
SLICE Register Clock-To-Output Delay TCO 0.455 ns 9
Minimum Clock High or Low Time TCLKHL 0.3 ns 9
I/O Input Pad and Buffer Delay TIN 0.767 1.308 ns 9
Output Delay Buffer and Pad Delay TDO 1.421 2.14 ns 9
Output Buffer Disable Delay TXZ 0.867 1.322 ns 9
Output Buffer Enable Delay TZX 1.242 1.532 ns 9
Delay for a column interconnect with average loading TC 0.679 ns 9
Delay for a row interconnect with average loading TR 0.523 ns 9
Local Routing Delay TLOCAL 0.434 ns 9

CAD (KiCad official)

  • Symbol: AGRV2KL64
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: agrv2kl64-etched.step / agrv2kl64-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); agrv2kl64.step / agrv2kl64.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: AGM Microelectronics datasheet (18 pp, sha256 fac8c7af30f4496e, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF