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AG576SL144

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AGM Microelectronics CPLD/FPGA, LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AG576SL144

AGM Microelectronics · CPLD/FPGA · LQFP-144(20x20)

AG576SL144 from AGM Microelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
2 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
3 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
4 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
5 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
6 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
7 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
8 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
9 VDDIO1 power_in I/O supply for bank 1 (bank 1 must be powered for the device to enter user mode).
10 GNDIO power_in I/O ground for bank 1.
11 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
12 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
13 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
14 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
15 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
16 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
17 GNDC power_in Core ground.
18 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
19 VDDC power_in Core supply (VCCINT), monitored by the POR circuit which begins SRAM download at approximately 1.2 V.
20 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
21 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
22 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
23 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
24 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
25 VDDIO1 power_in I/O supply for bank 1 (bank 1 must be powered for the device to enter user mode).
26 GNDIO power_in I/O ground for bank 1.
27 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
28 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
29 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
30 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
31 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
32 I/O bidirectional User I/O pin in bank 1 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
33 TMS input JTAG test mode select pin of the IEEE 1149.1 interface, supporting 1.5-V, 1.8-V or 3.3-V I/O standards.
34 TDI input JTAG test data input pin of the IEEE 1149.1 interface, supporting 1.5-V, 1.8-V or 3.3-V I/O standards.
35 TCK input JTAG test clock pin of the IEEE 1149.1 interface, supporting 1.5-V, 1.8-V or 3.3-V I/O standards.
36 TDO output JTAG test data output pin of the IEEE 1149.1 interface, supporting 1.5-V, 1.8-V or 3.3-V I/O standards.
37 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
38 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
39 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
40 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
41 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
42 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
43 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
44 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
45 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
46 VDDF33 power_in 3.3-V supply pin (VDDF33) in bank 2; the datasheet gives no further description.
47 GNDIO power_in I/O ground for bank 2.
48 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
49 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
50 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
51 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
52 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
53 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
54 GNDC power_in Core ground.
55 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
56 VDDC power_in Core supply (VCCINT), monitored by the POR circuit which begins SRAM download at approximately 1.2 V.
57 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
58 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
59 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
60 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
61 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
62 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
63 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
64 VDDIO1 power_in I/O supply pin listed in bank 2 with the VDDIO1 name (bank 1 supply).
65 GNDIO power_in I/O ground for bank 2.
66 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
67 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
68 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
69 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
70 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
71 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
72 I/O bidirectional User I/O pin in bank 2 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
73 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
74 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
75 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
76 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
77 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
78 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
79 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
80 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
81 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
82 VDDIO2 power_in I/O supply for bank 3.
83 GNDIO power_in I/O ground for bank 3.
84 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
85 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
86 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
87 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
88 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
89 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
90 VDDC power_in Core supply (VCCINT), monitored by the POR circuit which begins SRAM download at approximately 1.2 V.
91 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
92 GNDC power_in Core ground.
93 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
94 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
95 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
96 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
97 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
98 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
99 GNDIO power_in I/O ground for bank 3.
100 VDDIO2 power_in I/O supply for bank 3.
101 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
102 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
103 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
104 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
105 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
106 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
107 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
108 I/O bidirectional User I/O pin in bank 3 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
109 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
110 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
111 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
112 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
113 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
114 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
115 GNDIO power_in I/O ground for bank 4.
116 VDDIO2 power_in I/O supply for bank 4 (VDDIO2).
117 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
118 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
119 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
120 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
121 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
122 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
123 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
124 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
125 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
126 VDDC power_in Core supply (VCCINT), monitored by the POR circuit which begins SRAM download at approximately 1.2 V.
127 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
128 GNDC power_in Core ground.
129 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
130 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
131 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
132 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
133 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
134 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
135 GNDIO power_in I/O ground for bank 4.
136 VDDIO2 power_in I/O supply for bank 4 (VDDIO2).
137 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
138 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
139 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
140 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
141 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
142 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
143 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.
144 I/O bidirectional User I/O pin in bank 4 supporting 3.3-V, 2.5-V, 1.8-V and 1.5-V logic levels.

Key specifications

Parameter Value
Manufacturer AGM Microelectronics
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating junction temperature TJ -40 100 °C 3
On-chip oscillator frequency 7 9 11 MHz 10
SLICE Combinatorial LUT Delay TLUT 1.111 ns 11
SLICE Register Clear Delay TCLR 0.032 ns 11
SLICE Register Preset Delay TPRE 0.408 ns 11
SLICE Register Setup TSU 0.664 ns 11
SLICE Register Hold TH -0.636 ns 11
SLICE Register Clock-To-Output Delay TCO 0.455 ns 11
Minimum Clock High or Low Time TCLKHL 0.3 ns 11
I/O Input Pad and Buffer Delay TIN 0.767 1.308 ns 11
Output Delay Buffer and Pad Delay TDO 1.421 2.14 ns 11
Output Buffer Disable Delay TXZ 0.867 1.322 ns 11
Output Buffer Enable Delay TZX 1.242 1.532 ns 11
Delay for a column interconnect with average loading TC 0.679 ns 11
Delay for a row interconnect with average loading TR 0.523 ns 11
Local Routing Delay TLOCAL 0.434 ns 11

CAD (KiCad official)

  • Symbol: AG576SL144
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: ag576sl144-etched.step / ag576sl144-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ag576sl144.step / ag576sl144.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: AGM Microelectronics datasheet (17 pp, sha256 fb172e9dfaf5cfd2, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF