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AG576SL100

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AGM Microelectronics CPLD/FPGA, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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AG576SL100

AGM Microelectronics · CPLD/FPGA · LQFP-100(14x14)

AG576SL100 from AGM Microelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O bidirectional General-purpose user I/O in bank 4.
2 I/O bidirectional General-purpose user I/O in bank 1.
3 I/O bidirectional General-purpose user I/O in bank 1.
4 I/O bidirectional General-purpose user I/O in bank 1.
5 I/O bidirectional General-purpose user I/O in bank 1.
6 I/O bidirectional General-purpose user I/O in bank 1.
7 I/O bidirectional General-purpose user I/O in bank 1.
8 I/O bidirectional General-purpose user I/O in bank 1.
9 VDDIO1 power_in I/O supply for bank 1 (3.3-V, 2.5-V, 1.8-V or 1.5-V logic levels supported).
10 GNDIO power_in I/O ground for bank 1.
11 GNDC power_in Core ground.
12 I/O bidirectional General-purpose user I/O in bank 1.
13 VDDC power_in Core supply (VCCINT) monitored by the power-on reset circuit.
14 I/O bidirectional General-purpose user I/O in bank 1.
15 I/O bidirectional General-purpose user I/O in bank 1.
16 I/O bidirectional General-purpose user I/O in bank 1.
17 I/O bidirectional General-purpose user I/O in bank 1.
18 I/O bidirectional General-purpose user I/O in bank 1.
19 I/O bidirectional General-purpose user I/O in bank 1.
20 I/O bidirectional General-purpose user I/O in bank 1.
21 I/O bidirectional General-purpose user I/O in bank 1.
22 TMS input JTAG test mode select pin (IEEE 1149.1) in bank 1, used for boundary scan and in-system programming.
23 TDI input JTAG test data input pin (IEEE 1149.1) in bank 1, used for boundary scan and in-system programming.
24 TCK input JTAG test clock pin (IEEE 1149.1) in bank 1, used for boundary scan and in-system programming.
25 TDO output JTAG test data output pin (IEEE 1149.1) in bank 1, used for boundary scan and in-system programming.
26 I/O bidirectional General-purpose user I/O in bank 2.
27 I/O bidirectional General-purpose user I/O in bank 2.
28 I/O bidirectional General-purpose user I/O in bank 2.
29 I/O bidirectional General-purpose user I/O in bank 2.
30 I/O bidirectional General-purpose user I/O in bank 2.
31 VDDF33 power_in 3.3-V supply pin (VDDF33) in bank 2; function not further described in the datasheet.
32 GNDIO power_in I/O ground for bank 2.
33 I/O bidirectional General-purpose user I/O in bank 2.
34 I/O bidirectional General-purpose user I/O in bank 2.
35 I/O bidirectional General-purpose user I/O in bank 2.
36 I/O bidirectional General-purpose user I/O in bank 2.
37 I/O bidirectional General-purpose user I/O in bank 2.
38 I/O bidirectional General-purpose user I/O in bank 2.
39 I/O bidirectional General-purpose user I/O in bank 2.
40 I/O bidirectional General-purpose user I/O in bank 2.
41 I/O bidirectional General-purpose user I/O in bank 2.
42 I/O bidirectional General-purpose user I/O in bank 2.
43 I/O bidirectional General-purpose user I/O in bank 2.
44 I/O bidirectional General-purpose user I/O in bank 2.
45 VDDIO1 power_in I/O supply labelled VDDIO1 on a bank 2 pin (3.3-V, 2.5-V, 1.8-V or 1.5-V logic levels supported).
46 GNDIO power_in I/O ground for bank 2.
47 I/O bidirectional General-purpose user I/O in bank 2.
48 I/O bidirectional General-purpose user I/O in bank 2.
49 I/O bidirectional General-purpose user I/O in bank 2.
50 I/O bidirectional General-purpose user I/O in bank 2.
51 I/O bidirectional General-purpose user I/O in bank 2.
52 I/O bidirectional General-purpose user I/O in bank 3.
53 I/O bidirectional General-purpose user I/O in bank 3.
54 I/O bidirectional General-purpose user I/O in bank 3.
55 I/O bidirectional General-purpose user I/O in bank 3.
56 I/O bidirectional General-purpose user I/O in bank 3.
57 I/O bidirectional General-purpose user I/O in bank 3.
58 I/O bidirectional General-purpose user I/O in bank 3.
59 VDDIO2 power_in I/O supply for bank 3 (3.3-V, 2.5-V, 1.8-V or 1.5-V logic levels supported).
60 GNDIO power_in I/O ground for bank 3.
61 I/O bidirectional General-purpose user I/O in bank 3.
62 I/O bidirectional General-purpose user I/O in bank 3.
63 VDDC power_in Core supply (VCCINT) monitored by the power-on reset circuit.
64 I/O bidirectional General-purpose user I/O in bank 3.
65 GNDC power_in Core ground.
66 I/O bidirectional General-purpose user I/O in bank 3.
67 I/O bidirectional General-purpose user I/O in bank 3.
68 I/O bidirectional General-purpose user I/O in bank 3.
69 I/O bidirectional General-purpose user I/O in bank 3.
70 I/O bidirectional General-purpose user I/O in bank 3.
71 I/O bidirectional General-purpose user I/O in bank 3.
72 I/O bidirectional General-purpose user I/O in bank 3.
73 I/O bidirectional General-purpose user I/O in bank 3.
74 I/O bidirectional General-purpose user I/O in bank 3.
75 I/O bidirectional General-purpose user I/O in bank 3.
76 I/O bidirectional General-purpose user I/O in bank 4.
77 I/O bidirectional General-purpose user I/O in bank 4.
78 I/O bidirectional General-purpose user I/O in bank 4.
79 GNDIO power_in I/O ground for bank 4.
80 VDDIO2 power_in I/O supply for bank 4 (3.3-V, 2.5-V, 1.8-V or 1.5-V logic levels supported).
81 I/O bidirectional General-purpose user I/O in bank 4.
82 I/O bidirectional General-purpose user I/O in bank 4.
83 I/O bidirectional General-purpose user I/O in bank 4.
84 I/O bidirectional General-purpose user I/O in bank 4.
85 I/O bidirectional General-purpose user I/O in bank 4.
86 I/O bidirectional General-purpose user I/O in bank 4.
87 I/O bidirectional General-purpose user I/O in bank 4.
88 I/O bidirectional General-purpose user I/O in bank 4.
89 I/O bidirectional General-purpose user I/O in bank 4.
90 I/O bidirectional General-purpose user I/O in bank 4.
91 I/O bidirectional General-purpose user I/O in bank 4.
92 I/O bidirectional General-purpose user I/O in bank 4.
93 GNDIO power_in I/O ground for bank 4.
94 VDDIO2 power_in I/O supply for bank 4 (3.3-V, 2.5-V, 1.8-V or 1.5-V logic levels supported).
95 I/O bidirectional General-purpose user I/O in bank 4.
96 I/O bidirectional General-purpose user I/O in bank 4.
97 I/O bidirectional General-purpose user I/O in bank 4.
98 I/O bidirectional General-purpose user I/O in bank 4.
99 I/O bidirectional General-purpose user I/O in bank 4.
100 I/O bidirectional General-purpose user I/O in bank 4.

Key specifications

Parameter Value
Manufacturer AGM Microelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating junction temperature TJ -40 100 ℃ 3
On-chip oscillator frequency 7 9 11 MHz On-chip oscillator 10
SLICE Combinatorial LUT Delay TLUT 1.111 ns 11
SLICE Register Clear Delay TCLR 0.032 ns 11
SLICE Register Preset Delay TPRE 0.408 ns 11
SLICE Register Setup TSU 0.664 ns 11
SLICE Register Hold TH -0.636 ns 11
SLICE Register Clock-To-Output Delay TCO 0.455 ns 11
Minimum Clock High or Low Time TCLKHL 0.3 ns 11
I/O Input Pad and Buffer Delay TIN 0.767 1.308 ns 11
Output Delay Buffer and Pad Delay TDO 1.421 2.14 ns 11
Output Buffer Disable Delay TXZ 0.867 1.322 ns 11
Output Buffer Enable Delay TZX 1.242 1.532 ns 11
Delay for a column interconnect with average loading TC 0.679 ns 11
Delay for a row interconnect with average loading TR 0.523 ns 11
Local Routing Delay TLOCAL 0.434 ns 11

CAD (KiCad official)

  • Symbol: AG576SL100
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: ag576sl100-etched.step / ag576sl100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ag576sl100.step / ag576sl100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: AGM Microelectronics datasheet (17 pp, sha256 fb172e9dfaf5cfd2, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF