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AG32VF303KCU6

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AGM Microelectronics Microcontrollers (MCU/MPU/SOC), QFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AG32VF303KCU6

AGM Microelectronics · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(4x4)

AG32VF303KCU6 from AGM Microelectronics, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PIN_1 bidirectional General-purpose I/O that is also the RTC function pin (IO/RTC); the provided text gives no electrical limits for this pin.
2 PIN_2 bidirectional General-purpose I/O multiplexed with OSC_IN (the external oscillator input); the provided text gives no electrical limits for this pin.
3 PIN_3 bidirectional General-purpose I/O multiplexed with OSC_OUT (the external oscillator output); the provided text gives no electrical limits for this pin.
4 NRST input Active-low reset input for the MCU; the provided text gives no electrical limits for this pin.
5 PIN_5 bidirectional General-purpose I/O multiplexed with ADC_IN12; the provided text gives no electrical limits for this pin.
6 VDDA33 power_in Analog supply pin (labelled VDDA33 in the QFN-32 table); the provided text gives no voltage range for this pin.
7 PIN_7 bidirectional General-purpose I/O multiplexed with WKUP, ADC_IN0 and CMP_PA0; the provided text gives no electrical limits for this pin.
8 PIN_8 bidirectional General-purpose I/O multiplexed with ADC_IN1 and CMP_PA1; the provided text gives no electrical limits for this pin.
9 PIN_9 bidirectional General-purpose I/O multiplexed with ADC_IN2 and CMP_PA2; the provided text gives no electrical limits for this pin.
10 PIN_10 bidirectional General-purpose I/O multiplexed with ADC_IN3 and CMP_PA3; the provided text gives no electrical limits for this pin.
11 PIN_11 bidirectional General-purpose I/O multiplexed with ADC_IN4, CMP_PA4 and DAC0; the provided text gives no electrical limits for this pin.
12 PIN_12 bidirectional General-purpose I/O multiplexed with ADC_IN5, CMP_PA5 and DAC1; the provided text gives no electrical limits for this pin.
13 PIN_13 bidirectional General-purpose I/O multiplexed with ADC_IN6; the provided text gives no electrical limits for this pin.
14 PIN_14 bidirectional General-purpose I/O multiplexed with ADC_IN7; the provided text gives no electrical limits for this pin.
15 PIN_15 bidirectional General-purpose I/O multiplexed with the BOOT1 function; the provided text gives no electrical limits for this pin.
16 VDD33 power_in Main 3.3 V-class digital supply pin; the provided text gives no voltage range for this pin.
17 GND power_in Ground pin.
18 PIN_18 bidirectional General-purpose I/O; the provided text gives no electrical limits for this pin.
19 PIN_19 bidirectional General-purpose I/O; the provided text gives no electrical limits for this pin.
20 PIN_20 bidirectional General-purpose I/O multiplexed with the UART0_TX function; the provided text gives no electrical limits for this pin.
21 PIN_21 bidirectional General-purpose I/O multiplexed with the UART0_RX function; the provided text gives no electrical limits for this pin.
22 PIN_22 bidirectional General-purpose I/O multiplexed with the USBDM (USB D-) function; the provided text gives no electrical limits for this pin.
23 PIN_23 bidirectional General-purpose I/O multiplexed with the USBDP (USB D+) function; the provided text gives no electrical limits for this pin.
24 PIN_24 bidirectional General-purpose I/O multiplexed with the JTMS (JTAG/SWD mode select) function; the provided text gives no electrical limits for this pin.
25 PIN_25 bidirectional General-purpose I/O multiplexed with the JTCK (JTAG clock) function; the provided text gives no electrical limits for this pin.
26 PIN_26 bidirectional General-purpose I/O multiplexed with the JTDI (JTAG data in) function; the provided text gives no electrical limits for this pin.
27 PIN_27 bidirectional General-purpose I/O multiplexed with the JTDO (JTAG data out) function; the provided text gives no electrical limits for this pin.
28 PIN_28 bidirectional General-purpose I/O multiplexed with the JNTRST (JTAG reset) function; the provided text gives no electrical limits for this pin.
29 PIN_29 bidirectional General-purpose I/O; the provided text gives no electrical limits for this pin.
30 BOOT0 input Boot mode selection input (BOOT0); the provided text gives no electrical limits for this pin.
31 PIN_31 bidirectional General-purpose I/O; the provided text gives no electrical limits for this pin.
32 VDD33 power_in Main 3.3 V-class digital supply pin; the provided text gives no voltage range for this pin.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer AGM Microelectronics
Package QFN-32-EP(4x4)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 3 3.3 3.6 V 291
Analog supply voltage VDDA 3 3.3 3.6 V 291
Battery supply voltage VBAT 2.2 3.6 V 291
Maximum current for GPIO pins Iio 25 mA 291
Injected current on I/O Iinj -5 5 mA 291
Operating temperature range TA -40 85 °C 291
Storage temperature range TSTG -55 150 °C 291
Maximum junction temperature TJ 125 °C 291
Power on reset threshold Vpor 2 2.2 2.4 V 293
Power down reset threshold Vpdr 1.8 2 2.2 V 293
Maximum ESD voltage (human body model) VESD(HBM) 2000 V 292
Maximum ESD voltage (charge device model) VESD(CDM) 500 V 292
Latch-up LU 100 mA 292
Number of guaranteed program/erase cycles before failure (Endurance) PECYC 100 kcycles TA=-40°C ~ +85°C 296
Data retention time tRET 20 years TA=125°C 296
Word programming time tPROG 2 3 ms TA=-40°C ~ +85°C 296
Page erase time tERASE 8 20 ms TA=-40°C ~ +85°C 296
Mass erase time tMERASE 8 20 ms TA=-40°C ~ +85°C 296
Standard IO Low level input voltage VIL -0.3 0.8 V VDD ≥ 3.0V 296
Standard IO High level input voltage VIH 1.5 3.6 V VDD ≥ 3.0V 296
Low level output voltage VOL 0.2 V VDD ≥ 3.0V 296
High level output voltage VOH 2.8 V VDD ≥ 3.0V 296
Internal pull-up resistor RPU 30 40 50 kΩ VIN=VSS 296
Internal pull-down resistor RPD 30 40 50 kΩ VIN=VDD 296
Operating voltage VDDA 3 3.3 3.6 V 297
ADC clock fADC 0.5 13 MHz 297
Sampling rate fs 1 MHz 297
ADC conversion time tconv 1 20 μs 297
Input sampling switch resistance RADC 0.5 kΩ 297
Startup time tsu 2 μs 297
Operating voltage (DAC) VDDA 3 3.3 3.6 V 297
Reference supply voltage VREFP 3 3.3 3.6 V VREFP should always below VDDA 297
Load resistance RLOAD 5 kΩ Resistive load vs. VSSA with buffer ON 297
Load capacitance CLOAD 50 pF No pin/pad capacitance included 297
Analog supply voltage (comparator) VDDA 3 3.3 3.6 V 298
Comparator startup time tstart 10 μs VDDA ≥ 3.0 V 298
Propagation delay for full range step with 100 mV overdrive tD 40 ns VDDA ≥ 3.0 V 298
Comparator offset error VOFFSET -25 25 mV VDDA ≥ 3.0 V 298
SCL clock frequency fSCL 0 100 KHz 298
SCL clock high time tSCL(H) 4 0.6 ns 298
SCL clock low time tSCL(L) 4.7 1.3 ns 298
SCK clock high time tSCK(H) 5 ns 299
SCK clock low time tSCK(L) 5 ns 299
Data output valid time tV(MO) 5 ns SPI master mode 299
Data output hold time tH(MO) 2 ns SPI master mode 299
Data input setup time tSU(MI) 5 ns SPI master mode 299
Data input hold time tH(MI) 5 ns SPI master mode 299
NRST weak pull-up equivalent resistor RPU 30 40 50 kΩ VIN = VSS 300
NRST input filtered pulse VF(NRST) 100 ns 300
NRST input not filtered pulse VNF(NRST) 500 ns 300
HSE oscillator duty cycle Dosc_out 45 50 55 % 294
HSI oscillator frequency f_HSI 10 20 40 MHz VDD=3.3V 295
PLL input clock fPLL_IN 4 20 50 MHz 295
PLL multiplier output clock fPLL_OUT 2 200 300 MHz 295
PLL lock time tLOCK 400 μs 295
Cycle-to-cycle jitter Jitter 400 ps 295
Output high level voltage (USB) VOH 2.8 3.3 3.6 V RL of 15 kΩ to VSS 302

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pet Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter 76

CAD (KiCad official)

  • Symbol: AG32VF303KCU6
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: ag32vf303kcu6-etched.step / ag32vf303kcu6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ag32vf303kcu6.step / ag32vf303kcu6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: AGM Microelectronics datasheet (309 pp, sha256 bf24e7338ac0d2a9, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF