AFE881H1RRUR

{
  "slug": "afe881h1rrur",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Analog Front End (AFE), UQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "afe881h1rrur",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "afe881h1rrur.kicad_sym",
    "afe881h1rrur.kicad_mod",
    "afe881h1rrur.glb",
    "afe881h1rrur.step",
    "afe881h1rrur.lbr",
    "docs/hero.png",
    "docs/afe881h1rrur-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "afe881h1rrur-hero.glb",
    "afe881h1rrur-hero.overlay.json"
  ],
  "component": {
    "mpn": "AFE881H1RRUR",
    "manufacturer": "Texas Instruments",
    "package": "UQFN-24(4x4)",
    "pin_count": 25,
    "category": "Data Acquisition",
    "subcategory": "Analog Front End (AFE)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603011459601211392",
    "parts": {
      "symbol": "afe881h1rrur.kicad_sym",
      "footprint": "afe881h1rrur.kicad_mod",
      "model_3d": "afe881h1rrur-hero.glb",
      "model_3d_plain": "afe881h1rrur.glb",
      "model_3d_step": "afe881h1rrur-etched.step",
      "model_3d_step_plain": "afe881h1rrur.step",
      "lbr": "afe881h1rrur.lbr"
    },
    "distributor_links": {
      "lcsc": "C20345193",
      "digikey": "296-AFE881H1RRURTR-ND",
      "mouser": "595-AFE881H1RRUR"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T21:25:29Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-AFE881H1RRURTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-AFE881H1RRUR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "UARTIN",
        "type": "input",
        "description": "UART data input for the HART modem; connect to IOVDD or logic high if not used, and do not leave it floating."
      },
      {
        "number": "2",
        "name": "UARTOUT",
        "type": "output",
        "description": "UART data output that can be configured to function as the IRQ pin in SPI-only mode."
      },
      {
        "number": "3",
        "name": "CD",
        "type": "output",
        "description": "Carrier-detect output; a logic high indicates a valid HART carrier is present."
      },
      {
        "number": "4",
        "name": "RTS",
        "type": "input",
        "description": "Request-to-send input; logic high enables the demodulator and disables the modulator, and it must not be left floating."
      },
      {
        "number": "5",
        "name": "REF_EN",
        "type": "input",
        "description": "Internal VREF enable; logic high enables the internal reference (VREFIO outputs 1.25 V), and logic low requires an external 1.25-V reference at VREFIO."
      },
      {
        "number": "6",
        "name": "RESET",
        "type": "input",
        "description": "Reset input; logic low places the device in power-down mode and resets it, and logic high returns it to normal operation; must not be left floating."
      },
      {
        "number": "7",
        "name": "SCLK",
        "type": "input",
        "description": "SPI serial clock input (Schmitt-trigger) supporting rates up to 12.5 MHz; connect to GND or logic low if not used."
      },
      {
        "number": "8",
        "name": "SDI",
        "type": "input",
        "description": "SPI data input (Schmitt-trigger) clocked into the 24-bit input shift register on the falling SCLK edge; must not be left floating."
      },
      {
        "number": "9",
        "name": "SDO",
        "type": "output",
        "description": "SPI data output driven on the rising SCLK edge while CS is low; also the IRQ pin in UART break mode, Hi-Z at power-up until enabled in the CONFIG register."
      },
      {
        "number": "10",
        "name": "CS",
        "type": "input",
        "description": "SPI chip select; data is clocked in while CS is low, and when CS is high SDO is Hi-Z and SDI is ignored; must not be left floating."
      },
      {
        "number": "11",
        "name": "CLK_OUT",
        "type": "output",
        "description": "Clock output that can be configured to output the 1.2288-MHz internal clock."
      },
      {
        "number": "12",
        "name": "IOVDD",
        "type": "power_in",
        "description": "Interface supply for digital input and output circuitry, specified 1.71 V to 5.5 V, which sets the logic thresholds of the digital interfaces."
      },
      {
        "number": "13",
        "name": "VDD",
        "type": "power_out",
        "description": "Internal supply node; with 2.7 V to 5.5 V on PVDD the internal LDO drives it (connect a 1-µF to 10-µF capacitor), and with 1.71 V to 1.89 V on PVDD an external supply must be applied here."
      },
      {
        "number": "14",
        "name": "GND",
        "type": "power_in",
        "description": "Digital and analog ground, the ground reference point for all circuitry on the device."
      },
      {
        "number": "15",
        "name": "AIN0",
        "type": "input",
        "description": "ADC input voltage with a range of 0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V."
      },
      {
        "number": "16",
        "name": "POL_SEL/AIN1",
        "type": "input",
        "description": "ADC input AIN1 (0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V) when SPECIAL_CFG.AIN1_ENB = 1; otherwise it sets the polarity of the VOUT alarm voltage (ALMV_POL)."
      },
      {
        "number": "17",
        "name": "PVDD",
        "type": "power_in",
        "description": "Supply for the internal LDO, ADC input and VOUT DAC; 2.7 V to 5.5 V enables the internal LDO, while 1.71 V to 1.89 V disables it."
      },
      {
        "number": "18",
        "name": "VOUT",
        "type": "output",
        "description": "DAC output voltage; the device is specified for 0.15 V to 1.25 V or 0.2 V to 1.0 V output ranges at 1.8-V PVDD and 0.3 V to 2.5 V or 0.4 V to 2.0 V at 5-V PVDD."
      },
      {
        "number": "19",
        "name": "VREFIO",
        "type": "bidirectional",
        "description": "Outputs the internal 1.25-V reference when REF_EN is high (requires a 70-nF to 130-nF load capacitance for stability), and accepts an external 1.2 V to 1.3 V reference when REF_EN is low."
      },
      {
        "number": "20",
        "name": "REF_GND",
        "type": "power_in",
        "description": "Ground reference for the VREFIO pin."
      },
      {
        "number": "21",
        "name": "RX_IN",
        "type": "input",
        "description": "HART FSK input when no external filter is used; do not connect any signal to this pin when an external band-pass filter is used."
      },
      {
        "number": "22",
        "name": "RX_INF",
        "type": "input",
        "description": "HART FSK input for an external band-pass filter; when the internal band-pass filter is used by driving RX_IN, connect a 680-pF capacitor to this pin."
      },
      {
        "number": "23",
        "name": "MOD_OUT",
        "type": "output",
        "description": "FSK output sinusoid; maximum supported parallel load capacitance is 2 nF."
      },
      {
        "number": "24",
        "name": "ALARM",
        "type": "output",
        "description": "Open-drain alarm notification; held low when an alarm condition is asserted, otherwise high-impedance (Hi-Z)."
      },
      {
        "number": "25",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin 13 (VDD) is printed as P/AO in Table 5-1. I mapped it to power_out because the internal LDO driv; VREFIO is printed as AI/AO and can be either a reference output (REF_EN high) or an external referen; POL_SEL/AIN1 is printed as DI/AI and is a digital input for alarm polarity or an analog ADC input de",
          "exposed pad 25 added from the footprint"
        ],
        "pages_sent": 23,
        "cost_usd": 0.1476,
        "at": "2026-10-08T21:25:11"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603011459601211392",
        "pages": 112,
        "sha256": "8ab7592274e79b3b",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 25,
        "described": 25,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "afe881h1rrur.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.0,
          4.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f7d256794c4147daf24dcae0554fae18510315e565ad1e239b475be7fef80d8b",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "afe881h1rrur-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.0,
          4.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "b99fc0bc91f0542f9c41ac99ec7ee2c1d8190d62ccf24c4e1fa07d469e071060",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}