AFE881H1RRUR

Texas Instruments · Analog Front End (AFE) · UQFN-24(4x4)

AFE881H1RRUR from Texas Instruments, in a UQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	UARTIN	input	UART data input for the HART modem; connect to IOVDD or logic high if not used, and do not leave it floating.
2	UARTOUT	output	UART data output that can be configured to function as the IRQ pin in SPI-only mode.
3	CD	output	Carrier-detect output; a logic high indicates a valid HART carrier is present.
4	RTS	input	Request-to-send input; logic high enables the demodulator and disables the modulator, and it must not be left floating.
5	REF_EN	input	Internal VREF enable; logic high enables the internal reference (VREFIO outputs 1.25 V), and logic low requires an external 1.25-V reference at VREFIO.
6	RESET	input	Reset input; logic low places the device in power-down mode and resets it, and logic high returns it to normal operation; must not be left floating.
7	SCLK	input	SPI serial clock input (Schmitt-trigger) supporting rates up to 12.5 MHz; connect to GND or logic low if not used.
8	SDI	input	SPI data input (Schmitt-trigger) clocked into the 24-bit input shift register on the falling SCLK edge; must not be left floating.
9	SDO	output	SPI data output driven on the rising SCLK edge while CS is low; also the IRQ pin in UART break mode, Hi-Z at power-up until enabled in the CONFIG register.
10	CS	input	SPI chip select; data is clocked in while CS is low, and when CS is high SDO is Hi-Z and SDI is ignored; must not be left floating.
11	CLK_OUT	output	Clock output that can be configured to output the 1.2288-MHz internal clock.
12	IOVDD	power_in	Interface supply for digital input and output circuitry, specified 1.71 V to 5.5 V, which sets the logic thresholds of the digital interfaces.
13	VDD	power_out	Internal supply node; with 2.7 V to 5.5 V on PVDD the internal LDO drives it (connect a 1-µF to 10-µF capacitor), and with 1.71 V to 1.89 V on PVDD an external supply must be applied here.
14	GND	power_in	Digital and analog ground, the ground reference point for all circuitry on the device.
15	AIN0	input	ADC input voltage with a range of 0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V.
16	POL_SEL/AIN1	input	ADC input AIN1 (0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V) when SPECIAL_CFG.AIN1_ENB = 1; otherwise it sets the polarity of the VOUT alarm voltage (ALMV_POL).
17	PVDD	power_in	Supply for the internal LDO, ADC input and VOUT DAC; 2.7 V to 5.5 V enables the internal LDO, while 1.71 V to 1.89 V disables it.
18	VOUT	output	DAC output voltage; the device is specified for 0.15 V to 1.25 V or 0.2 V to 1.0 V output ranges at 1.8-V PVDD and 0.3 V to 2.5 V or 0.4 V to 2.0 V at 5-V PVDD.
19	VREFIO	bidirectional	Outputs the internal 1.25-V reference when REF_EN is high (requires a 70-nF to 130-nF load capacitance for stability), and accepts an external 1.2 V to 1.3 V reference when REF_EN is low.
20	REF_GND	power_in	Ground reference for the VREFIO pin.
21	RX_IN	input	HART FSK input when no external filter is used; do not connect any signal to this pin when an external band-pass filter is used.
22	RX_INF	input	HART FSK input for an external band-pass filter; when the internal band-pass filter is used by driving RX_IN, connect a 680-pF capacitor to this pin.
23	MOD_OUT	output	FSK output sinusoid; maximum supported parallel load capacitance is 2 nF.
24	ALARM	output	Open-drain alarm notification; held low when an alarm condition is asserted, otherwise high-impedance (Hi-Z).
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	UQFN-24(4x4)
Category	Data Acquisition
Pins	25

CAD (KiCad official)

Symbol: AFE881H1RRUR
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: UQFN-24(4x4) (KiCad packages3D, STEP)
3D model files: afe881h1rrur-etched.step / afe881h1rrur-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); afe881h1rrur.step / afe881h1rrur.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (112 pp, sha256 8ab7592274e79b3b, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AFE881H1RRUR

**Texas Instruments** · Analog Front End (AFE) · UQFN-24(4x4)

AFE881H1RRUR from Texas Instruments, in a UQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | UARTIN | input | UART data input for the HART modem; connect to IOVDD or logic high if not used, and do not leave it floating. |
| 2 | UARTOUT | output | UART data output that can be configured to function as the IRQ pin in SPI-only mode. |
| 3 | CD | output | Carrier-detect output; a logic high indicates a valid HART carrier is present. |
| 4 | RTS | input | Request-to-send input; logic high enables the demodulator and disables the modulator, and it must not be left floating. |
| 5 | REF_EN | input | Internal VREF enable; logic high enables the internal reference (VREFIO outputs 1.25 V), and logic low requires an external 1.25-V reference at VREFIO. |
| 6 | RESET | input | Reset input; logic low places the device in power-down mode and resets it, and logic high returns it to normal operation; must not be left floating. |
| 7 | SCLK | input | SPI serial clock input (Schmitt-trigger) supporting rates up to 12.5 MHz; connect to GND or logic low if not used. |
| 8 | SDI | input | SPI data input (Schmitt-trigger) clocked into the 24-bit input shift register on the falling SCLK edge; must not be left floating. |
| 9 | SDO | output | SPI data output driven on the rising SCLK edge while CS is low; also the IRQ pin in UART break mode, Hi-Z at power-up until enabled in the CONFIG register. |
| 10 | CS | input | SPI chip select; data is clocked in while CS is low, and when CS is high SDO is Hi-Z and SDI is ignored; must not be left floating. |
| 11 | CLK_OUT | output | Clock output that can be configured to output the 1.2288-MHz internal clock. |
| 12 | IOVDD | power_in | Interface supply for digital input and output circuitry, specified 1.71 V to 5.5 V, which sets the logic thresholds of the digital interfaces. |
| 13 | VDD | power_out | Internal supply node; with 2.7 V to 5.5 V on PVDD the internal LDO drives it (connect a 1-µF to 10-µF capacitor), and with 1.71 V to 1.89 V on PVDD an external supply must be applied here. |
| 14 | GND | power_in | Digital and analog ground, the ground reference point for all circuitry on the device. |
| 15 | AIN0 | input | ADC input voltage with a range of 0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V. |
| 16 | POL_SEL/AIN1 | input | ADC input AIN1 (0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V) when SPECIAL_CFG.AIN1_ENB = 1; otherwise it sets the polarity of the VOUT alarm voltage (ALMV_POL). |
| 17 | PVDD | power_in | Supply for the internal LDO, ADC input and VOUT DAC; 2.7 V to 5.5 V enables the internal LDO, while 1.71 V to 1.89 V disables it. |
| 18 | VOUT | output | DAC output voltage; the device is specified for 0.15 V to 1.25 V or 0.2 V to 1.0 V output ranges at 1.8-V PVDD and 0.3 V to 2.5 V or 0.4 V to 2.0 V at 5-V PVDD. |
| 19 | VREFIO | bidirectional | Outputs the internal 1.25-V reference when REF_EN is high (requires a 70-nF to 130-nF load capacitance for stability), and accepts an external 1.2 V to 1.3 V reference when REF_EN is low. |
| 20 | REF_GND | power_in | Ground reference for the VREFIO pin. |
| 21 | RX_IN | input | HART FSK input when no external filter is used; do not connect any signal to this pin when an external band-pass filter is used. |
| 22 | RX_INF | input | HART FSK input for an external band-pass filter; when the internal band-pass filter is used by driving RX_IN, connect a 680-pF capacitor to this pin. |
| 23 | MOD_OUT | output | FSK output sinusoid; maximum supported parallel load capacitance is 2 nF. |
| 24 | ALARM | output | Open-drain alarm notification; held low when an alarm condition is asserted, otherwise high-impedance (Hi-Z). |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | UQFN-24(4x4) |
| Category | Data Acquisition |
| Pins | 25 |

## CAD (KiCad official)

- Symbol: `AFE881H1RRUR`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`
- 3D model: UQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files: `afe881h1rrur-etched.step` / `afe881h1rrur-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `afe881h1rrur.step` / `afe881h1rrur.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603011459601211392) (112 pp, sha256 `8ab7592274e79b3b`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/afe881h1rrur-datasheet.pdf)