component

AFE5401TRGCTQ1

Public Made by Adom

by adom

Texas Instruments Analog Front End (AFEs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionafe5401trgctq1factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

AFE5401TRGCTQ1

Texas Instruments · Analog Front End (AFEs) · VQFN-64-EP(9x9)

AFE5401TRGCTQ1 from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1P_AUX input Positive differential auxiliary analog input pin for channel 1.
2 IN1M_AUX input Negative differential auxiliary analog input pin for channel 1.
3 IN1P input Positive differential analog input pin for channel 1.
4 IN1M input Negative differential analog input pin for channel 1.
5 IN2P_AUX input Positive differential auxiliary analog input pin for channel 2.
6 IN2M_AUX input Negative differential auxiliary analog input pin for channel 2.
7 IN2P input Positive differential analog input pin for channel 2.
8 IN2M input Negative differential analog input pin for channel 2.
9 IN3P_AUX input Positive differential auxiliary analog input pin for channel 3.
10 IN3M_AUX input Negative differential auxiliary analog input pin for channel 3.
11 IN3P input Positive differential analog input pin for channel 3.
12 IN3M input Negative differential analog input pin for channel 3.
13 IN4P_AUX input Positive differential auxiliary analog input pin for channel 4.
14 IN4M_AUX input Negative differential auxiliary analog input pin for channel 4.
15 IN4P input Positive differential analog input pin for channel 4.
16 IN4M input Negative differential analog input pin for channel 4.
17 VCM output Output pin for the common-mode bias voltage of the auxiliary input signals.
18 AVDD3 power_in 3.3-V analog supply voltage.
19 AVDD18 power_in 1.8-V analog supply voltage.
20 AVSS power_in Analog ground.
21 CLKINP input Positive differential clock input pin; a single-ended clock is also supported.
22 CLKINM input Negative differential clock input pin; a single-ended clock is also supported.
23 AVSS power_in Analog ground.
24 AVDD18 power_in 1.8-V analog supply voltage.
25 TRIG input Trigger for DSYNC1 and DSYNC2; has an internal 150-kΩ pull-down resistor.
26 DSYNC1 output Data synchronization clock 1.
27 DSYNC2 output Data synchronization clock 2.
28 DVDD18 power_in 1.8-V digital supply voltage.
29 DVSS power_in Digital ground.
30 DVDD18 power_in 1.8-V digital supply voltage.
31 DRVSS power_in CMOS output driver ground.
32 DRVDD power_in CMOS output driver supply.
33 DRVDD power_in CMOS output driver supply.
34 DCLK output CMOS output clock.
35 D[11] output CMOS output data bit 11 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
36 D[10] output CMOS output data bit 10 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
37 D[9] output CMOS output data bit 9 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
38 D[8] output CMOS output data bit 8 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
39 D[7] output CMOS output data bit 7 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
40 D[6] output CMOS output data bit 6 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
41 D[5] output CMOS output data bit 5 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
42 D[4] output CMOS output data bit 4 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
43 D[3] output CMOS output data bit 3 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
44 D[2] output CMOS output data bit 2 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
45 D[1] output CMOS output data bit 1 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
46 D[0] output CMOS output data bit 0 for channels 1 to 4 (12-bit parallel output bus D[11:0] on pins 35-46).
47 D_GPO[1] output General-purpose CMOS output.
48 D_GPO[0] output General-purpose CMOS output.
49 DRVSS power_in CMOS output driver ground.
50 DRVDD power_in CMOS output driver supply.
51 DVDD18 power_in 1.8-V digital supply voltage.
52 DVSS power_in Digital ground.
53 SDOUT output Serial interface data readout.
54 SEN input Serial interface enable; has an internal 150-kΩ pull-up resistor.
55 SDATA input Serial interface data input; has an internal 150-kΩ pull-down resistor.
56 SCLK input Serial interface clock input; has an internal 150-kΩ pull-down resistor.
57 RESET input Hardware reset pin (active high); has an internal 150-kΩ pull-down resistor.
58 NC unconnected Do not connect.
59 STBY input Standby control input; has an internal 150-kΩ pull-down resistor.
60 NC unconnected Do not connect.
61 AVSS power_in Analog ground.
62 AVDD18 power_in 1.8-V analog supply voltage.
63 AVSS power_in Analog ground.
64 VCM output Output pin for the common-mode bias voltage of the auxiliary input signals.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category ADC/DAC/Data Conversion
Pins 65

CAD (KiCad official)

  • Symbol: AFE5401TRGCTQ1
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: afe5401trgctq1-etched.step / afe5401trgctq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); afe5401trgctq1.step / afe5401trgctq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (79 pp, sha256 d48174ee6dd9b9fc, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF