# ADX111QAMSOP10

**analogysemi** · Analog To Digital Converters (ADC) · MSOP-10

ADX111QAMSOP10 from analogysemi, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ADDR | input | I2C slave address select pin, connected to GND, VDD, SDA or SCL to choose one of four addresses (1001000, 1001001, 1001010, 1001011), and its state is sampled continuously. |
| 2 | ALERT/RDY | output | Open-drain comparator output or conversion-ready output that requires a pull-up resistor to VDD, and may be left floating or weakly pulled up if unused. |
| 3 | GND | power_in | Ground reference for the device. |
| 4 | AIN0 | passive | Analog input 0, which must be kept within GND - 0.3 V to VDD + 0.3 V to avoid forward-biasing the ESD diodes. |
| 5 | AIN1 | passive | Analog input 1, which must be kept within GND - 0.3 V to VDD + 0.3 V to avoid forward-biasing the ESD diodes. |
| 6 | AIN2 | passive | Analog input 2, which must be kept within GND - 0.3 V to VDD + 0.3 V to avoid forward-biasing the ESD diodes. |
| 7 | AIN3 | passive | Analog input 3, which must be kept within GND - 0.3 V to VDD + 0.3 V to avoid forward-biasing the ESD diodes. |
| 8 | VDD | power_in | Power supply, which must be decoupled to GND with a 0.1 µF capacitor. |
| 9 | SDA | bidirectional | Serial data line that transmits and receives data, and requires an external pull-up resistor because the I2C driver is open-drain. |
| 10 | SCL | input | Serial clock input that locks data on SDA, and the device never drives this line low (no clock stretching). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | analogysemi |
| Package | MSOP-10 |
| Category | Data Acquisition |
| Pins | 10 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Data Rate Variation |  | -7 |  | 6 | % | All data rates | 6 |
| Integral Nonlinearity | INL |  | 0.5 | 1 | LSB | DR = 8SPS, FSR = ±2.048V | 6 |
| Offset Error (differential inputs) |  | -2 | 0 | 2 | LSB | FSR = ±2.048V, differential inputs | 6 |
| Offset Error (single-ended inputs) |  | -2 |  | 2 | LSB | FSR = ±2.048V, single-ended inputs | 6 |
| Gain Error |  |  | 0.01 | 0.1 | % | FSR = ±2.048V, TA = 25°C | 6 |
| Gain Drift Over Temperature |  |  | 8 | 30 | ppm/°C | FSR = ±2.048V | 6 |
| Long-Term Gain Drift |  | -0.05 |  | 0.05 | % | FSR = ±2.048V, TA = 125°C, 1000 hrs | 6 |
| Gain Match |  |  | 0.01 | 0.05 | % | Match between any two gains | 6 |
| Gain Channel Match |  |  | 0.03 | 0.05 | % | Match between any two inputs | 6 |
| Common-Mode Rejection Ratio | CMRR | 110 |  |  | dB | At DC, FSR = ±0.256V | 6 |
| Common-Mode Rejection Ratio | CMRR | 105 |  |  | dB | At DC, FSR = ±2.048V | 6 |
| Common-Mode Rejection Ratio | CMRR | 100 |  |  | dB | At DC, FSR = ±6.144V | 6 |
| Common-Mode Rejection Ratio | CMRR | 103 |  |  | dB | fCM = 60Hz, DR = 8SPS | 6 |
| Common-Mode Rejection Ratio | CMRR | 104 |  |  | dB | fCM = 50Hz, DR = 8SPS | 6 |
| High-Level Input Voltage | VIH |  |  | 5.5 | V |  | 6 |
| Low-Level Output Voltage | VOL |  | 0.15 | 0.4 | V | IOL = 3mA | 6 |
| Input Leakage Current |  | -10 |  | 10 | µA | GND < VDIG < VDD | 6 |
| Supply Current, power-down | IVDD |  | 0.65 | 1 | µA | Power-down, TA = 25°C | 7 |
| Supply Current, power-down | IVDD |  |  | 3.5 | µA | Power-down | 7 |
| Supply Current, operating | IVDD |  | 145 | 170 | µA | Operating, TA = 25°C | 7 |
| Supply Current, operating | IVDD |  |  | 300 | µA | Operating | 7 |
| Power-Supply Voltage (recommended) | VDD | 2 |  | 5.5 | V |  | 5 |
| Full-Scale Input Voltage Range | FSR | 0.256 |  | 6.144 | V | VIN = V(AINP), V(AINN) | 5 |
| Digital Input Voltage (recommended) | VDIG |  |  | 5.5 | V |  | 5 |
| Operating Ambient Temperature (recommended) | TA | -40 |  | 125 | °C |  | 5 |
| Power-Supply Voltage VDD to GND | VDD | -0.3 |  | 7 | V |  | 4 |
| Digital Input Voltage (SDA, SCL, ADDR, ALERT/RDY) |  |  |  | 5.5 | V |  | 4 |
| Input Current, Continuous |  | -10 |  | 10 | mA | Any pin except power supply pins | 4 |
| Operating Ambient Temperature | TA | -40 |  | 125 | °C |  | 4 |
| Junction Temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage Temperature | Tstg | -60 |  | 150 | °C |  | 4 |
| SCL Clock Frequency | fSCL | 0.01 |  | 0.4 | MHz | Fast mode | 8 |
| SCL Clock Frequency | fSCL | 0.01 |  | 3.4 | MHz | High-speed mode | 8 |
| Bus Free Time Between START and STOP Condition | tBUF | 600 |  |  | ns | Fast mode | 8 |
| Bus Free Time Between START and STOP Condition | tBUF | 160 |  |  | ns | High-speed mode | 8 |
| Hold Time After Repeated START Condition | tHDSTA | 600 |  |  | ns | Fast mode | 8 |
| Hold Time After Repeated START Condition | tHDSTA | 160 |  |  | ns | High-speed mode | 8 |
| Setup Time for A Repeated START Condition | tSUSTA | 600 |  |  | ns | Fast mode | 8 |
| Setup Time for A Repeated START Condition | tSUSTA | 160 |  |  | ns | High-speed mode | 8 |
| Setup Time for STOP Condition | tSUSTO | 600 |  |  | ns | Fast mode | 8 |
| Setup Time for STOP Condition | tSUSTO | 160 |  |  | ns | High-speed mode | 8 |
| Data Hold Time | tHDDAT | 0 |  |  | ns | Fast mode | 8 |
| Data Setup Time | tSUDAT | 100 |  |  | ns | Fast mode | 8 |
| Data Setup Time | tSUDAT | 10 |  |  | ns | High-speed mode | 8 |
| Low Period of the SCL Clock Pin | tLOW | 1300 |  |  | ns | Fast mode | 8 |
| Low Period of the SCL Clock Pin | tLOW | 160 |  |  | ns | High-speed mode | 8 |
| High Period for the SCL Clock Pin | tHIGH | 600 |  |  | ns | Fast mode | 8 |
| High Period for the SCL Clock Pin | tHIGH | 60 |  |  | ns | High-speed mode | 8 |
| Rise Time for Both SDA and SCL Signals | tF |  |  | 300 | ns | Fast mode | 8 |
| Rise Time for Both SDA and SCL Signals | tF |  |  | 160 | ns | High-speed mode | 8 |
| Fall Time for Both SDA and SCL Signals | tR |  |  | 300 | ns | Fast mode | 8 |
| Fall Time for Both SDA and SCL Signals | tR |  |  | 160 | ns | High-speed mode | 8 |
| Junction-to-Ambient Thermal Resistance (MSOP-10) | RθJA |  | 150 |  | °C/W |  | 5 |
| Junction-to-Case (Top) Thermal Resistance (MSOP-10) | RθJC(top) |  | 54 |  | °C/W |  | 5 |
| Junction-to-Board Thermal Resistance (MSOP-10) | RθJB |  | 90 |  | °C/W |  | 5 |
| Junction-to-Top Characterization Parameter (MSOP-10) | ψJT |  | 3 |  | °C/W |  | 5 |
| Junction-to-Board Characterization Parameter (MSOP-10) | ψJB |  | 86 |  | °C/W |  | 5 |
| Junction-to-Case (Bottom) Thermal Resistance (MSOP-10) | RθJC(bot) |  | 90 |  | °C/W |  | 5 |

## CAD (KiCad official)

- Symbol: `ADX111QAMSOP10`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `adx111qamsop10-etched.step` / `adx111qamsop10-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adx111qamsop10.step` / `adx111qamsop10.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [analogysemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603062999310102528) (39 pp, sha256 `433863d98d6f473e`, retrieved 2026-10-20, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/adx111qamsop10-datasheet.pdf)