component
ADV7513BSWZ
Public Made by Adomby adom
Analog Devices Video Interface ICs, LQFP-64(10x10). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownADV7513BSWZ
Analog Devices · Video Interface ICs · LQFP-64(10x10)
ADV7513BSWZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVDD | power_in | 1.8 V Power Supply; should be filtered and as quiet as possible |
| 2 | VSYNC | input | Vertical Synchronization Input for digital video |
| 3 | SPDIF | input | S/PDIF (Sony/Philips Digital Interface) Audio Input |
| 4 | MCLK | input | Audio Reference Clock Input |
| 5 | I2S0 | input | I2S Channel 0 Audio Data Input |
| 6 | I2S1 | input | I2S Channel 1 Audio Data Input |
| 7 | I2S2 | input | I2S Channel 2 Audio Data Input |
| 8 | I2S3 | input | I2S Channel 3 Audio Data Input |
| 9 | SCLK | input | I2S Audio Clock Input |
| 10 | LRCLK | input | Left/Right Channel Signal Input for I2S audio |
| 11 | DVDD | power_in | 1.8 V Power Supply; should be filtered and as quiet as possible |
| 12 | PVDD | power_in | 1.8 V PLL Power Supply |
| 13 | BGVDD | power_in | 1.8 V Band Gap Power Supply |
| 14 | R_EXT | input | Reference current setting pin; sets the internal reference currents |
| 15 | AVDD | power_in | 1.8 V Power Supply for TMDS Outputs |
| 16 | HPD | input | Hot Plug Detect Signal Input; tolerates 1.3 V to 5.5 V |
| 17 | TXC− | output | Differential TMDS Clock Output (negative); TMDS differential swing 800-1200 mV |
| 18 | TXC+ | output | Differential TMDS Clock Output (positive); TMDS differential swing 800-1200 mV |
| 19 | AVDD | power_in | 1.8 V Power Supply for TMDS Outputs |
| 20 | TX0− | output | Differential TMDS Output Channel 0 (negative); TMDS differential swing 800-1200 mV |
| 21 | TX0+ | output | Differential TMDS Output Channel 0 (positive); TMDS differential swing 800-1200 mV |
| 22 | PD | input | Power-Down Control and I2C Address Selection input |
| 23 | TX1− | output | Differential TMDS Output Channel 1 (negative); TMDS differential swing 800-1200 mV |
| 24 | TX1+ | output | Differential TMDS Output Channel 1 (positive); TMDS differential swing 800-1200 mV |
| 25 | AVDD | power_in | 1.8 V Power Supply for TMDS Outputs |
| 26 | TX2− | output | Differential TMDS Output Channel 2 (negative); TMDS differential swing 800-1200 mV |
| 27 | TX2+ | output | Differential TMDS Output Channel 2 (positive); TMDS differential swing 800-1200 mV |
| 28 | INT | output | Interrupt Signal Output for reporting HDMI events |
| 29 | DVDD_3V | power_in | 3.3 V Power Supply |
| 30 | CEC | bidirectional | CEC Data Signal (open-drain); tolerates 2.0 V to 5.5 V input |
| 31 | DVDD | power_in | 1.8 V Power Supply; should be filtered and as quiet as possible |
| 32 | CEC_CLK | input | CEC Clock (Oscillator) Input; frequency 3 MHz to 100 MHz |
| 33 | DDCSCL | bidirectional | DDC Serial Port Data Clock to Sink (open-drain); tolerates 1.4 V to 5.5 V |
| 34 | DDCSDA | bidirectional | DDC Serial Port Data Input/Output to Sink (open-drain); tolerates 1.4 V to 5.5 V |
| 35 | SCL | bidirectional | I2C Serial Port Data Clock Input (open-drain); tolerates 1.4 V to 5.5 V |
| 36 | SDA | bidirectional | I2C Serial Port Data Input/Output (open-drain); tolerates 1.4 V to 5.5 V |
| 37 | D0 | input | Video Data Input bit 0; input logic levels 1.8 V to 3.3 V |
| 38 | D1 | input | Video Data Input bit 1; input logic levels 1.8 V to 3.3 V |
| 39 | D2 | input | Video Data Input bit 2; input logic levels 1.8 V to 3.3 V |
| 40 | D3 | input | Video Data Input bit 3; input logic levels 1.8 V to 3.3 V |
| 41 | D4 | input | Video Data Input bit 4; input logic levels 1.8 V to 3.3 V |
| 42 | D5 | input | Video Data Input bit 5; input logic levels 1.8 V to 3.3 V |
| 43 | D6 | input | Video Data Input bit 6; input logic levels 1.8 V to 3.3 V |
| 44 | D7 | input | Video Data Input bit 7; input logic levels 1.8 V to 3.3 V |
| 45 | D8 | input | Video Data Input bit 8; input logic levels 1.8 V to 3.3 V |
| 46 | D9 | input | Video Data Input bit 9; input logic levels 1.8 V to 3.3 V |
| 47 | D10 | input | Video Data Input bit 10; input logic levels 1.8 V to 3.3 V |
| 48 | D11 | input | Video Data Input bit 11; input logic levels 1.8 V to 3.3 V |
| 49 | D12 | input | Video Data Input bit 12; input logic levels 1.8 V to 3.3 V |
| 50 | D13 | input | Video Data Input bit 13; input logic levels 1.8 V to 3.3 V |
| 51 | DVDD | power_in | 1.8 V Power Supply; should be filtered and as quiet as possible |
| 52 | D14 | input | Video Data Input bit 14; input logic levels 1.8 V to 3.3 V |
| 53 | CLK | input | Video Input Clock; frequency up to 165 MHz |
| 54 | D15 | input | Video Data Input bit 15; input logic levels 1.8 V to 3.3 V |
| 55 | D16 | input | Video Data Input bit 16; input logic levels 1.8 V to 3.3 V |
| 56 | D17 | input | Video Data Input bit 17; input logic levels 1.8 V to 3.3 V |
| 57 | D18 | input | Video Data Input bit 18; input logic levels 1.8 V to 3.3 V |
| 58 | D19 | input | Video Data Input bit 19; input logic levels 1.8 V to 3.3 V |
| 59 | D20 | input | Video Data Input bit 20; input logic levels 1.8 V to 3.3 V |
| 60 | D21 | input | Video Data Input bit 21; input logic levels 1.8 V to 3.3 V |
| 61 | D22 | input | Video Data Input bit 22; input logic levels 1.8 V to 3.3 V |
| 62 | D23 | input | Video Data Input bit 23; input logic levels 1.8 V to 3.3 V |
| 63 | DE | input | Data Enable Signal for Digital Video input |
| 64 | HSYNC | input | Horizontal Synchronization Input |
| EPAD | GND | power_in | Exposed pad is the electrical ground for the part; must be soldered to PCB |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-64(10x10) |
| Category | Interface |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
ADV7513BSWZ - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
adv7513bswz-etched.step/adv7513bswz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adv7513bswz.step/adv7513bswz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (12 pp, sha256
94e6510bbdee8f74, retrieved 2026-09-29, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).