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ADUM7642CRQZ-RL7

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Analog Devices Digital Isolators, QSOP-20-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADUM7642CRQZ-RL7

Analog Devices · Digital Isolators · QSOP-20-150mil

ADUM7642CRQZ-RL7 from Analog Devices, in a QSOP-20-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1A power_in Side 1 supply voltage A (3.0 V to 5.5 V) must be externally connected to pin 7 and bypassed with 0.01 µF to 0.1 µF to GND1 (pin 2).
2 GND1 power_in Side 1 ground reference, internally connected to pin 10; both pins should be connected to the side 1 PCB ground.
3 VIA input Logic input A on side 1; input thresholds are VIH = 0.7 VDDx and VIL = 0.3 VDDx.
4 VIB input Logic input B on side 1; input thresholds are VIH = 0.7 VDDx and VIL = 0.3 VDDx.
5 VIC input Logic input C on side 1; input thresholds are VIH = 0.7 VDDx and VIL = 0.3 VDDx.
6 VOD output Logic output D on side 2; it defaults to high when the input side is unpowered and goes high-impedance when the output-side supply is unpowered.
7 VDD1B power_in Side 1 supply voltage B (3.0 V to 5.5 V) must be externally connected to pin 1 and bypassed with 0.01 µF to 0.1 µF to GND1 (pin 10).
8 VOE output Logic output E on side 2; it defaults to high when the input side is unpowered and goes high-impedance when the output-side supply is unpowered.
9 VIF input Logic input F on side 1; input thresholds are VIH = 0.7 VDDx and VIL = 0.3 VDDx.
10 GND1 power_in Side 1 ground reference, internally connected to pin 2; both pins should be connected to the side 1 PCB ground.
11 GND2 power_in Side 2 ground reference, internally connected to pin 19; both pins should be connected to the side 2 PCB ground.
12 VOF output Logic output F on side 2; it defaults to high when the input side is unpowered and goes high-impedance when the output-side supply is unpowered.
13 VIE input Logic input E on side 1; input thresholds are VIH = 0.7 VDDx and VIL = 0.3 VDDx.
14 VDD2B power_in Side 2 supply voltage B (3.0 V to 5.5 V) must be externally connected to pin 20 and bypassed with 0.01 µF to 0.1 µF to GND2 (pin 11).
15 VID input Logic input D on side 2; input thresholds are VIH = 0.7 VDDx and VIL = 0.3 VDDx.
16 VOC output Logic output C on side 2; it defaults to high when the input side is unpowered and goes high-impedance when the output-side supply is unpowered.
17 VOB output Logic output B on side 2; it defaults to high when the input side is unpowered and goes high-impedance when the output-side supply is unpowered.
18 VOA output Logic output A on side 2; it defaults to high when the input side is unpowered and goes high-impedance when the output-side supply is unpowered.
19 GND2 power_in Side 2 ground reference, internally connected to pin 11; both pins should be connected to the side 2 PCB ground.
20 VDD2A power_in Side 2 supply voltage A (3.0 V to 5.5 V) must be externally connected to pin 14 and bypassed with 0.01 µF to 0.1 µF to GND2 (pin 19).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package QSOP-20-150mil
Category Signal Isolation Devices
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating temperature TA -40 105 °C 9
Supply voltage VDD1, VDD2 3 5.5 V 9
Input signal rise and fall time 1 ms 9
Storage temperature range TST -65 150 °C 10
Operating ambient temperature TA -40 105 °C 10
Supply voltage VDD1, VDD2 -0.5 7 V 10
Input voltage VIA, VIB, VIC, VID, VIE, VIF -0.5 V max printed as VDDI + 0.5 V 10
Output voltage VOA, VOB, VOC, VOD, VIE, VIF -0.5 V max printed as VDDO + 0.5 V 10
Average output current per pin, side 1 IO1 -10 10 mA 10
Average output current per pin, side 2 IO2 -10 10 mA 10
IC junction-to-ambient thermal resistance θJA 76 °C/W thermocouple located at center of package underside 9
Resistance (input to output) RI-O 1013 Ω 9
Capacitance (input to output) CI-O 2 pF f = 1 MHz 9
Input capacitance CI 4 pF 9
Propagation delay (5 V) tPHL, tPLH 28 40 50 ns 50%输入至50%输出 3
Minimum pulse width (5 V) PW 40 ns 在PWD限值内 3
Data rate (5 V) 25 Mbps 在PWD限值内 3
Pulse width distortion (5 V) PWD 2 6 ns /tPLH − tPHL/ 3
Temperature rate of change (5 V) 3 ps/°C 3
Propagation delay skew (5 V) tPSK 14 ns 3
Channel matching, same direction (5 V) tPSKCD 6 12 ns 3
Channel matching, opposite direction (5 V) tPSKOD 7 12 ns 3
Jitter (5 V) 2 ns 3
Supply current, side 1, 1 Mbps (5 V) IDD1 5.2 6.3 mA 无负载; 1 Mbps 3
Supply current, side 1, 25 Mbps (5 V) IDD1 31 38 mA 无负载; 25 Mbps 3
Supply current, side 2, 1 Mbps (5 V) IDD2 4.8 6 mA 无负载; 1 Mbps 3
Supply current, side 2, 25 Mbps (5 V) IDD2 19 24 mA 无负载; 25 Mbps 3
Logic high output voltage (5 V) VOH 5 V IOx = −20 µA, VIx = VIxH 4
Logic high output voltage (5 V) VOH 4.8 V IOx = −4 mA, VIx = VIxH 4
Logic low output voltage (5 V) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 4
Logic low output voltage (5 V) VOL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 4
Input current per channel II -10 0.01 10 µA 0 V ≤ VIx ≤ VDDx 4
Quiescent input supply current per channel (5 V) IDDI (Q) 0.95 1.16 mA 4
Quiescent output supply current per channel (5 V) IDDO (Q) 0.73 0.98 mA 4
Output rise/fall time (5 V) tR/tF 2 ns 10%至90% 4
Common-mode transient immunity (5 V) /CM/ 15 25 kV/µs VIx = VDDx, VCM = 1000 V, 瞬变幅度 = 800 V 4
Refresh rate (5 V) fr 600 kHz DC数据输入 4
Propagation delay (3.3 V) tPHL, tPLH 33 49 66 ns 50%输入至50%输出 5
Minimum pulse width (3.3 V) PW 40 ns 在PWD限值内 5
Data rate (3.3 V) 25 Mbps 在PWD限值内 5
Pulse width distortion (3.3 V) PWD 2 6 ns /tPLH − tPHL/ 5
Temperature rate of change (3.3 V) 3 ps/°C 5
Propagation delay skew (3.3 V) tPSK 14 ns 5
Channel matching, same direction (3.3 V) tPSKCD 6 15 ns 5
Channel matching, opposite direction (3.3 V) tPSKOD 6 15 ns 5
Jitter (3.3 V) 2 ns 5
Supply current, side 1, 1 Mbps (3.3 V) IDD1 3.7 4.7 mA 无负载; 1 Mbps 5
Supply current, side 1, 25 Mbps (3.3 V) IDD1 23 27 mA 无负载; 25 Mbps 5
Supply current, side 2, 1 Mbps (3.3 V) IDD2 3.5 4.4 mA 无负载; 1 Mbps 5
Supply current, side 2, 25 Mbps (3.3 V) IDD2 14 16 mA 无负载; 25 Mbps 5
Logic high output voltage (3.3 V) VOH 3.3 V IOx = −20 µA, VIx = VIxH 6
Logic high output voltage (3.3 V) VOH 3.1 V IOx = −4 mA, VIx = VIxH 6
Logic low output voltage (3.3 V) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 6
Logic low output voltage (3.3 V) VOL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 6
Input current per channel (3.3 V) II -10 0.01 10 µA 0 V ≤ VIx ≤ VDDx 6
Quiescent input supply current per channel (3.3 V) IDDI (Q) 0.68 0.87 mA 6
Quiescent output supply current per channel (3.3 V) IDDO (Q) 0.55 0.72 mA 6
Output rise/fall time (3.3 V) tR/tF 2.8 ns 10%至90% 6
Common-mode transient immunity (3.3 V) /CM/ 15 20 kV/µs VIx = VDDx, VCM = 1000 V, 瞬变幅度 = 800 V 6
Refresh rate (3.3 V) fr 550 kHz DC数据输入 6

CAD (KiCad official)

  • Symbol: ADUM7642CRQZ-RL7
  • Footprint: Package_SO:QSOP-20_3.9x8.7mm_P0.635mm
  • 3D model: QSOP-20-150mil (KiCad packages3D, STEP)
  • 3D model files: adum7642crqz-rl7-etched.step / adum7642crqz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum7642crqz-rl7.step / adum7642crqz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (20 pp, sha256 70463431aa383d36, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF