ADUM6020-5WBRIZ from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NIC	unconnected	No internal connection; leave this pin floating.
2	GND1	power_in	Primary-side ground reference; recommended to be connected to a common ground with the other GND1 pins.
3	PDIS	input	Power disable: tied to any GND1 pin the VISO output is active, a logic high shuts down VISO; do not leave floating.
4	GND1	power_in	Primary-side ground reference; recommended to be connected to a common ground with the other GND1 pins.
5	VDDP	power_in	Primary supply voltage; the supply range is 4.5 V to 5.5 V for the ADuM6020-5 models.
6	GND1	power_in	Primary-side ground reference; recommended to be connected to a common ground with the other GND1 pins.
7	NIC	unconnected	No internal connection; leave this pin floating.
8	GND1	power_in	Primary-side ground reference; recommended to be connected to a common ground with the other GND1 pins.
9	GNDISO	power_in	Ground reference for VISO on side 2; recommended to be connected to a common ground with the other GNDISO pins.
10	NIC	unconnected	No internal connection; leave this pin floating.
11	GNDISO	power_in	Ground reference for VISO on side 2; recommended to be connected to a common ground with the other GNDISO pins.
12	VISO	power_out	Secondary supply voltage output for external loads (up to 100 mA for the ADuM6020).
13	GNDISO	power_in	Ground reference for VISO on side 2; recommended to be connected to a common ground with the other GNDISO pins.
14	VSEL	input	Output voltage selection: connect to VISO for 5 V output or to GNDISO for 3.3 V output; weak internal pull-up, do not leave floating.
15	GNDISO	power_in	Ground reference for VISO on side 2; recommended to be connected to a common ground with the other GNDISO pins.
16	NIC	unconnected	No internal connection; leave this pin floating.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-16
Category	Power Management
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VISO setpoint (5 V output)	VISO	4.75	5	5.25	V	VISO output current (IISO) = 10 mA	4
Load regulation (5 V output)	VISO (LOAD)		1	5	%	IISO = 10 mA to 90 mA	4
VDDP no-load supply current (5 V output)	IDDP (Q)		8	25	mA	No VISO load	4
VDDP UVLO rising threshold (5 V output)		3.6	4.1	4.4	V	Undervoltage lockout, VDDP rising	4
VDDP UVLO falling threshold (5 V output)		2.8	3.3	4.2	V	Undervoltage lockout, VDDP falling	4
Output supply current (5 V output)	IISO (MAX)	50			mA	4.75 V < VISO < 5.25 V	4
Output supply current (5 V output, extended)	IISO (MAX)	100			mA	4.5 V < VISO < 5.25 V	4
VISO setpoint (3.3 V output)	VISO	3.135	3.3	3.465	V	IISO = 10 mA	5
Load regulation (3.3 V output)	VISO (LOAD)		1	5	%	IISO = 10 mA to 90 mA	5
VDDP no-load supply current (3.3 V output)	IDDP (Q)		5	18	mA	No VISO load	5
VDDP UVLO rising threshold (3.3 V output)		3.6	4.1	4.4	V	Undervoltage lockout, VDDP rising	5
VDDP UVLO falling threshold (3.3 V output)		2.8	3.3	4.2	V	Undervoltage lockout, VDDP falling	5
Output supply current (3.3 V output)	IISO (MAX)	50			mA	3.135 V < VISO < 3.465 V	5
Output supply current (3.3 V output, extended)	IISO (MAX)	100			mA	3.0 V < VISO < 3.465 V	5
Operating temperature	TA	-40		125	°C	Operation at >85°C requires reduction of the maximum load current	12
Supply voltage VDDP (VISO = 3.135 V to 3.465 V)	VDDP	4.5		5.5	V	ADuM6020-5BRIZ, VDDP at VISO = 3.135 V to 3.465 V	12
Supply voltage VDDP (VISO = 4.75 V to 5.25 V)	VDDP	4.5		5.5	V	ADuM6020-5BRIZ, VDDP at VISO = 4.75 V to 5.25 V	12
Storage temperature	TST	-55		150	°C	TA = 25°C	13
Ambient operating temperature	TA	-40		125	°C	TA = 25°C	13
Supply voltages	VDDP, VISO	-0.5		7	V	Relative to respective ground	13
VISO supply current (ADuM6020)				100	mA	ADuM6020	13
Input voltage (PDIS, VSEL)		-0.5		5.5	V	-0.5 V to VDDP + 0.5 V; VDDP is input side supply voltage	13
Common-mode transients		-200		200	kV/µs	Across the insulation barrier	13
Maximum continuous working voltage, AC bipolar				565	V peak	Bipolar waveform, reinforced insulation rating per IEC 60747-17 (VDE 0884-17)	13
Line regulation (5 V output)	VISO (LINE)		2		mV/V	IISO = 50 mA, VDDP = 4.5 V to 5.5 V	4
Output ripple (5 V output)	VISO (RIP)		75		mV p-p	20 MHz bandwidth, bypass output capacitance (CBO) = 0.1 µF//10 µF, IISO = 90 mA	4
Output noise (5 V output)	VISO (NOISE)		200		mV p-p	CBO = 0.1 µF//10 µF, IISO = 90 mA	4
Switching frequency	fOSC		180		MHz		4
PWM frequency	fPWM		625		kHz		4
Efficiency at IISO (MAX) (5 V output)			33		%	IISO = 100 mA, TA = 25°C	4
VDDP full-load supply current (5 V output)	IDDP (MAX)		310		mA	Full VISO load	4
VISO UVLO rising threshold (5 V output)			5.1		V	Undervoltage lockout, VISO rising	4
VISO UVLO falling threshold (5 V output)			2.48		V	Undervoltage lockout, VISO falling	4
Thermal shutdown temperature			154		°C		4
Thermal hysteresis			10		°C		4
Line regulation (3.3 V output)	VISO (LINE)		2		mV/V	IISO = 50 mA, VDDP = 3.0 V to 3.6 V	5
Output ripple (3.3 V output)	VISO (RIP)		50		mV p-p	20 MHz bandwidth, CBO = 0.1 µF//10 µF, IISO = 90 mA	5
Output noise (3.3 V output)	VISO (NOISE)		130		mV p-p	CBO = 0.1 µF//10 µF, IISO = 90 mA	5
Efficiency at IISO (MAX) (3.3 V output)			27		%	IISO = 100 mA, TA = 25°C	5
VDDP full-load supply current (3.3 V output)	IDDP (MAX)		250		mA	Full VISO load	5
VISO UVLO rising threshold (3.3 V output)			3.28		V	Undervoltage lockout, VISO rising	5
VISO UVLO falling threshold (3.3 V output)			2.45		V	Undervoltage lockout, VISO falling	5
Junction to ambient thermal resistance	θJA		45		°C/W	Thermocouple located at center of package underside; JEDEC JESD-51 2s2p board, still air	10
Input to output capacitance	CI-O		2.2		pF	f = 1 MHz	10
Input capacitance	CI		4		pF	Input capacitance is from any input data pin to ground	10
Rated dielectric insulation voltage	VISO		5000		V rms	1-minute duration	9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pC		In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM6020 and ADuM6028 are proof tested by applying an insulation test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5	8

CAD (KiCad official)

Symbol: ADUM6020-5WBRIZ
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: adum6020-5wbriz-etched.step / adum6020-5wbriz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum6020-5wbriz.step / adum6020-5wbriz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (23 pp, sha256 58cd90ef0c78c231, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADUM6020-5WBRIZ

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3D Model

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