ADUM5412BRSZ from Analog Devices, in a SSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Power supply for the Side 1 logic circuits, independent of VDDP and operating between 3.0 V and 5.5 V.
2	GND1	power_in	Ground 1 reference for the primary isolator; internally connected to Pin 9 and Pin 12 and recommended to be tied to a common ground.
3	VIA	input	Logic Input A.
4	VIB	input	Logic Input B.
5	VOC	output	Logic Output C.
6	VOD	output	Logic Output D.
7	VE1	input	Output Enable 1: VOC and VOD outputs are enabled when high or disconnected and disabled when low; tie to a logic level in noisy environments.
8	NIC	unconnected	No internal connection; leave floating.
9	GND1	power_in	Ground 1 reference for the primary isolator; internally connected to Pin 2 and Pin 12 and recommended to be tied to a common ground.
10	PDIS	input	Power Disable: converter is active when tied to any GND1 pin, and a logic high puts the supply in low power standby mode.
11	VDDP	power_in	Primary supply voltage, 3.0 V to 5.5 V.
12	GND1	power_in	Ground 1 reference for the primary isolator; internally connected to Pin 2 and Pin 9 and recommended to be tied to a common ground.
13	GNDISO	power_in	Ground reference for VDD2 and VISO on Side 2; internally connected to Pin 16 and Pin 23 and recommended to be tied to a common ground.
14	VISO	power_out	Secondary supply voltage output for external loads; connect to VDD2 to power the isolator channels.
15	VSEL	input	Output voltage selection, set by a resistor network between VISO and GNDISO.
16	GNDISO	power_in	Ground reference for VDD2 and VISO on Side 2; internally connected to Pin 13 and Pin 23 and recommended to be tied to a common ground.
17	NIC	unconnected	No internal connection; leave floating.
18	VE2	input	Output Enable 2: VOA and VOB outputs are enabled when high or disconnected and disabled when low; tie to a logic level in noisy environments.
19	VID	input	Logic Input D.
20	VIC	input	Logic Input C.
21	VOB	output	Logic Output B.
22	VOA	output	Logic Output A.
23	GNDISO	power_in	Ground reference for VDD2 and VISO on Side 2; internally connected to Pin 13 and Pin 16 and recommended to be tied to a common ground.
24	VDD2	power_in	Power supply for the Side 2 logic circuits, independent of VDDP and operating between 3.0 V and 5.5 V.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SSOP-24
Category	Interface ICs
Pins	24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Output setpoint voltage (5V/5V)	VISO	4.7	5	5.4	V	IISO = 15 mA, R1 = 10 kΩ, R2 = 30.9 kΩ	3
Line regulation (5V/5V)	VISO (LINE)			20	mV/V	IISO = 15 mA, VDDP = 4.5 V to 5.5 V	3
Load regulation (5V/5V)	VISO (LOAD)		1	5	%	IISO = 3 mA to 27 mA	3
VDDP supply current, no VISO load (5V/5V)	IDDP (Q)		14	20	mA		3
VDDP supply current, full VISO load (5V/5V)	IDDP (MAX)		104	140	mA		3
ADuM5412 IDD1 supply current, 1 Mbps (5V)	IDD1		4.3	7.7	mA	CL = 0 pF, 1 Mbps	3
ADuM5412 IDD2 supply current, 1 Mbps (5V)	IDD2		5.3	8.7	mA	CL = 0 pF, 1 Mbps	3
ADuM5412 IDD1 supply current, 25 Mbps (5V)	IDD1		6	9.3	mA	CL = 0 pF, 25 Mbps	3
ADuM5412 IDD2 supply current, 25 Mbps (5V)	IDD2		6.7	10.1	mA	CL = 0 pF, 25 Mbps	3
ADuM5412 IDD1 supply current, 100 Mbps (5V)	IDD1		10.3	14.2	mA	CL = 0 pF, 100 Mbps	3
ADuM5412 IDD2 supply current, 100 Mbps (5V)	IDD2		11	14.9	mA	CL = 0 pF, 100 Mbps	3
Minimum pulse width (5V)	PW			6.6	ns	Within pulse width distortion (PWD) limit	3
Maximum data rate (5V)		150			Mbps	Within PWD limit	3
Propagation delay (5V)	tPHL, tPLH	4.8	7.2	13	ns	50% input to 50% output	3
Pulse width distortion (5V)	PWD		0.5	3	ns	/tPLH − tPHL/	3
Propagation delay skew (5V)	tPSK			6.1	ns	Between any two units at the same temperature, voltage, and load	3
Channel matching, codirectional (5V)	tPSKCD		0.5	3	ns		3
Channel matching, opposing direction (5V)	tPSKOD		0.5	3	ns		3
Input currents per channel	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx	4
Logic low output voltage, 20 µA	VOL	0		0.1	V	IOx = 20 µA, VIx = VIxL	4
Logic low output voltage, 4 mA	VOL	0		0.4	V	IOx = 4 mA, VIx = VIxL	4
ADuM5412 IDD1 quiescent, logic 0 (5V)	IDD1 (Q)		1.6	2.46	mA	VIx = Logic 0	4
ADuM5412 IDD2 quiescent, logic 0 (5V)	IDD2 (Q)		1.6	2.46	mA	VIx = Logic 0	4
ADuM5412 IDD1 quiescent, logic 1 (5V)	IDD1 (Q)		7.2	11.5	mA	VIx = Logic 1	4
ADuM5412 IDD2 quiescent, logic 1 (5V)	IDD2 (Q)		8.4	11.5	mA	VIx = Logic 1	4
Common-mode transient immunity, high	/CMH/	75	100		kV/µs	VIx = VDD1 or VISO, common-mode voltage (VCM) = 1000 V, transient magnitude = 800 V	4
Common-mode transient immunity, low	/CML/	75	100		kV/µs	VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V	4
Output setpoint voltage (5V in/3.3V out)	VISO	3	3.3	3.6	V	IISO = 15 mA, R1 = 10 kΩ, R2 = 16.9 kΩ	7
Load regulation (5V in/3.3V out)	VISO (LOAD)		1	5	%	IISO = 3 mA to 27 mA	7
VDDP supply current, full VISO load (5V in/3.3V out)	IDDP (MAX)		85	115	mA		7
Output setpoint voltage (3.3V/3.3V)	VISO	3	3.3	3.6	V	IISO = 10 mA, R1 = 10 kΩ, R2 = 16.9 kΩ	5
Propagation delay (3.3V/3.3V)	tPHL, tPLH		6.8	14	ns	50% input to 50% output	5
Input to output capacitance	CI-O		2.2		pF	f = 1 MHz	12
Input capacitance	CI		4		pF		12
Junction to ambient thermal resistance	θJA		50		°C/W	Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces	12
Rated dielectric insulation voltage	VISO		2500		V rms	1-minute duration	13
Operating temperature	TA	-40		105	°C		14
VDDP supply voltage at VISO = 3.0 V to 3.6 V	VDDP	3		5.5	V	VISO = 3.0 V to 3.6 V	14
VDDP supply voltage at VISO = 4.5 V to 5.5 V	VDDP	4.5		5.5	V	VISO = 4.5 V to 5.5 V	14
VDD1, VDD2 supply voltage	VDD1, VDD2	1.7		5.5	V		15
Storage temperature	TST	-55		150	°C		16
Ambient operating temperature	TA	-40		105	°C		16
Supply voltages	VDD1, VDDP, VDD2, VISO	-0.5		7	V	Relative to respective ground	16
VISO supply current				30	mA	TA = −40°C to +105°C	16
Input voltage		-0.5			V	VIA, VIB, VIC, VID, VE1, VE2, VSEL, PDIS: −0.5 V to VDDI + 0.5 V	16
Output voltage		-0.5			V	VOA, VOB, VOC, VOD: −0.5 V to VDDO + 0.5 V	16
Average output current per data output pin		-10		10	mA		16
Common-mode transients		-150		150	kV/µs	Across the insulation barrier	16

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pC		In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM5410/ADuM5411/ADuM5412 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limi	13

CAD (KiCad official)

Symbol: ADUM5412BRSZ
Footprint: Package_SO:SSOP-24_5.3x8.2mm_P0.65mm
3D model: SSOP-24 (KiCad packages3D, STEP)
3D model files: adum5412brsz-etched.step / adum5412brsz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum5412brsz.step / adum5412brsz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (30 pp, sha256 5762eced48c3a69d, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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ADUM5412BRSZ

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