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ADUM5411BRSZ

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Analog Devices Digital Isolators, SSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADUM5411BRSZ

Analog Devices · Digital Isolators · SSOP-24

ADUM5411BRSZ from Analog Devices, in a SSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Power supply for the side 1 logic circuits; independent of VDDP and operates between 3.0 V and 5.5 V.
2 GND1 power_in Ground 1, the ground reference for the primary isolator; pins 2, 9, and 12 are internally connected and should be tied to a common ground.
3 VIA input Logic Input A, the data input for isolation channel A.
4 VIB input Logic Input B, the data input for isolation channel B.
5 VIC input Logic Input C, the data input for isolation channel C.
6 VOD output Logic Output D, the data output for isolation channel D.
7 VE1 input Output Enable 1; when high or disconnected the VOD output is enabled, when low it is disabled, and connecting VE1 to either an external logic high or logic low is recommended in noisy environments.
8 NIC unconnected No Internal Connection; leave this pin floating.
9 GND1 power_in Ground 1, internally connected to pins 2 and 12 and recommended to be tied to a common ground.
10 PDIS input Power Disable; when tied to any GND1 pin the power converter is active, and when a logic high voltage is applied the power supply enters a low power standby mode.
11 VDDP power_in Primary Supply Voltage, 3.0 V to 5.5 V.
12 GND1 power_in Ground 1, internally connected to pins 2 and 9 and recommended to be tied to a common ground.
13 GNDISO power_in Ground reference for VDD2 and VISO on side 2; pins 13, 16, and 23 are internally connected and should be tied to a common ground.
14 VISO power_out Secondary supply voltage output for external loads; connect to VDD2 to power the isolator channels.
15 VSEL input Output Voltage Selection, which sets the VISO output voltage through the external resistor network described in the truth table.
16 GNDISO power_in Ground reference for VDD2 and VISO on side 2, internally connected to pins 13 and 23.
17 NIC unconnected No Internal Connection; leave this pin floating.
18 VE2 input Output Enable 2; when high or disconnected the VOA, VOB, and VOC outputs are enabled, and when low they are disabled.
19 VID input Logic Input D, the data input for isolation channel D on the side 2 domain.
20 VOC output Logic Output C, the data output for isolation channel C.
21 VOB output Logic Output B, the data output for isolation channel B.
22 VOA output Logic Output A, the data output for isolation channel A.
23 GNDISO power_in Ground reference for VDD2 and VISO on side 2, internally connected to pins 13 and 16.
24 VDD2 power_in Power supply for the side 2 logic circuits; independent of VDDP and operates between 3.0 V and 5.5 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SSOP-24
Category Interface ICs
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature TST -55 150 °C 16
Ambient Operating Temperature TA -40 105 °C 16
Supply Voltages (VDD1, VDDP, VDD2, VISO) VDD1, VDDP, VDD2, VISO -0.5 7 V Relative to respective ground 16
VISO Supply Current VISO 30 mA TA = −40°C to +105°C 16
Average Output Current Per Data Output Pin IO -10 10 mA 16
Common-Mode Transients -150 150 kV/µs Across the insulation barrier 16
Operating Temperature TA -40 105 °C 14
Supply Voltage VDDP at VISO = 3.0 V to 3.6 V VDDP 3 5.5 V VISO = 3.0 V to 3.6 V 14
Supply Voltage VDDP at VISO = 4.5 V to 5.5 V VDDP 4.5 5.5 V VISO = 4.5 V to 5.5 V 14
Supply Voltage VDD1, VDD2 VDD1, VDD2 1.7 5.5 V 15
Junction to Ambient Thermal Resistance θJA 50 °C/W Thermocouple at center of package underside, 4-layer board with thin traces 12
Input Capacitance CI 4 pF Any input data pin to ground 12
Capacitance (Input to Output) CI-O 2.2 pF f = 1 MHz 12
Setpoint VISO 4.7 5 5.4 V IISO = 15 mA, R1 = 10 kΩ, R2 = 30.9 kΩ 3
Load Regulation VISO (LOAD) 1 5 % IISO = 3 mA to 27 mA 3
Line Regulation VISO (LINE) 20 mV/V IISO = 15 mA, VDDP = 4.5 V to 5.5 V 3
Output Ripple VISO (RIP) 75 mV p-p 20 MHz bandwidth, CBO = 0.1 µF//10 µF, IISO = 27 mA 3
Output Noise VISO (NOISE) 200 mV p-p CBO = 0.1 µF//10 µF, IISO = 27 mA 3
Switching Frequency fOSC 125 MHz 3
Pulse-Width Modulation Frequency fPWM 600 kHz 3
Output Supply IISO (MAX) 30 mA VISO > 4.5 V 3
Efficiency at IISO (MAX) 29 % IISO = 27 mA 3
VDDP Supply Current, No VISO Load IDDP (Q) 14 20 mA No VISO Load 3
VDDP Supply Current, Full VISO Load IDDP (MAX) 104 140 mA Full VISO Load 3
Shutdown Temperature 154 °C Thermal shutdown 3
Thermal Hysteresis 10 °C Thermal shutdown 3
Propagation Delay tPHL, tPLH 4.8 7.2 13 ns 50% input to 50% output 3
Pulse Width Distortion PWD 0.5 3 ns /tPLH − tPHL/ 3
Propagation Delay Skew tPSK 6.1 ns Between any two units at the same temperature, voltage, and load 3
Pulse Width PW 6.6 ns Within pulse width distortion (PWD) limit 3
Data Rate 150 Mbps Within PWD limit 3
Jitter 490 ps p-p 4
Input Current per Channel II -10 0.01 10 µA 0 V ≤ VIx ≤ VDDx 4
Quiescent Supply Current ADuM5411, IDD1 (Q), Logic 0 IDD1 (Q) 1.6 2.46 mA VIx = Logic 0 4
Quiescent Supply Current ADuM5411, IDD2 (Q), Logic 0 IDD2 (Q) 1.9 2.62 mA VIx = Logic 0 4
Quiescent Supply Current ADuM5411, IDD1 (Q), Logic 1 IDD1 (Q) 10 17 mA VIx = Logic 1 4
Quiescent Supply Current ADuM5411, IDD2 (Q), Logic 1 IDD2 (Q) 6 10 mA VIx = Logic 1 4
Undervoltage Lockout Positive Going Threshold VUV+ 1.6 V VDD1, VDD2, and VDDP supply 4
Undervoltage Lockout Negative Going Threshold VUV− 1.5 V VDD1, VDD2, and VDDP supply 4
Dynamic Supply Current Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle 4
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% 4
Common-Mode Transient Immunity, High /CMH/ 75 100 kV/µs VIx = VDD1 or VISO, common-mode voltage (VCM) = 1000 V, transient magnitude = 800 V 4
Common-Mode Transient Immunity, Low /CML/ 75 100 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM5410/ADuM5411/ADuM5412 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limi 13

CAD (KiCad official)

  • Symbol: ADUM5411BRSZ
  • Footprint: Package_SO:SSOP-24_5.3x8.2mm_P0.65mm
  • 3D model: SSOP-24 (KiCad packages3D, STEP)
  • 3D model files: adum5411brsz-etched.step / adum5411brsz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum5411brsz.step / adum5411brsz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (30 pp, sha256 5762eced48c3a69d, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF