# ADUM5410BRSZ

**Analog Devices** · Digital Isolators · SSOP-24

ADUM5410BRSZ from Analog Devices, in a SSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Power supply for the Side 1 logic circuits, independent of VDDP, operating between 3.0 V and 5.5 V. |
| 2 | GND1 | power_in | Ground 1, ground reference for the primary isolator; internally connected to Pin 9 and Pin 12 and should be connected to a common ground. |
| 3 | VIA | input | Logic Input A. |
| 4 | VIB | input | Logic Input B. |
| 5 | VIC | input | Logic Input C. |
| 6 | VID | input | Logic Input D. |
| 7 | NIC | unconnected | No internal connection; leave this pin floating. |
| 8 | NIC | unconnected | No internal connection; leave this pin floating. |
| 9 | GND1 | power_in | Ground 1, ground reference for the primary isolator; internally connected to Pin 2 and Pin 12 and should be connected to a common ground. |
| 10 | PDIS | input | Power Disable: when tied to any GND1 pin the power converter is active, and when a logic high is applied the supply enters a low power standby mode. |
| 11 | VDDP | power_in | Primary supply voltage for the isoPower converter, 3.0 V to 5.5 V. |
| 12 | GND1 | power_in | Ground 1, ground reference for the primary isolator; internally connected to Pin 2 and Pin 9 and should be connected to a common ground. |
| 13 | GNDISO | power_in | Ground reference for VDD2 and VISO on Side 2; internally connected to Pin 16 and Pin 23 and should be connected to a common ground. |
| 14 | VISO | power_out | Secondary supply voltage output for external loads; connect to VDD2 to power the isolator channels. |
| 15 | VSEL | input | Output voltage selection, set by a resistor network between VISO and GNDISO (e.g. R1 = 10 kΩ, R2 = 30.9 kΩ for 5 V; R2 = 16.9 kΩ for 3.3 V). |
| 16 | GNDISO | power_in | Ground reference for VDD2 and VISO on Side 2; internally connected to Pin 13 and Pin 23 and should be connected to a common ground. |
| 17 | NIC | unconnected | No internal connection; leave this pin floating. |
| 18 | VE2 | input | Output Enable 2: VOA, VOB, VOC and VOD outputs are enabled when high or disconnected and disabled when low; tying to a logic level is recommended in noisy environments. |
| 19 | VOD | output | Logic Output D. |
| 20 | VOC | output | Logic Output C. |
| 21 | VOB | output | Logic Output B. |
| 22 | VOA | output | Logic Output A. |
| 23 | GNDISO | power_in | Ground reference for VDD2 and VISO on Side 2; internally connected to Pin 13 and Pin 16 and should be connected to a common ground. |
| 24 | VDD2 | power_in | Power supply for the Side 2 logic circuits, independent of VDDP, operating between 3.0 V and 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SSOP-24 |
| Category | Interface ICs |
| Pins | 24 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC-to-DC Setpoint | VISO | 4.7 | 5 | 5.4 | V | IISO = 15 mA, R1 = 10 kΩ, R2 = 30.9 kΩ | 3 |
| Load Regulation | VISO (LOAD) |  | 1 | 5 | % | IISO = 3 mA to 27 mA | 3 |
| Output Supply Current | IISO (MAX) |  |  | 30 | mA | VISO > 4.5 V | 3 |
| VDDP Supply Current, No VISO Load | IDDP (Q) |  | 14 | 20 | mA |  | 3 |
| VDDP Supply Current, Full VISO Load | IDDP (MAX) |  | 104 | 140 | mA |  | 3 |
| Output Ripple | VISO (RIP) |  | 75 |  | mV p-p | 20 MHz bandwidth, CBO = 0.1 µF//10 µF, IISO = 27 mA | 3 |
| Output Noise | VISO (NOISE) |  | 200 |  | mV p-p | CBO = 0.1 µF//10 µF, IISO = 27 mA | 3 |
| Efficiency at IISO (MAX) |  |  | 29 |  | % | IISO = 27 mA | 3 |
| Shutdown Temperature |  |  | 154 |  | °C |  | 3 |
| Thermal Hysteresis |  |  | 10 |  | °C |  | 3 |
| ADuM5410 IDD1 supply current, 1 Mbps | IDD1 |  | 6.8 | 10 | mA | CL = 0 pF, 1 Mbps | 3 |
| ADuM5410 IDD2 supply current, 1 Mbps | IDD2 |  | 2.1 | 3.7 | mA | CL = 0 pF, 1 Mbps | 3 |
| ADuM5410 IDD1 supply current, 25 Mbps | IDD1 |  | 7.8 | 12 | mA | CL = 0 pF, 25 Mbps | 3 |
| ADuM5410 IDD2 supply current, 25 Mbps | IDD2 |  | 3.9 | 5.7 | mA | CL = 0 pF, 25 Mbps | 3 |
| ADuM5410 IDD1 supply current, 100 Mbps | IDD1 |  | 11.8 | 17.4 | mA | CL = 0 pF, 100 Mbps | 3 |
| ADuM5410 IDD2 supply current, 100 Mbps | IDD2 |  | 9.2 | 13 | mA | CL = 0 pF, 100 Mbps | 3 |
| Pulse Width | PW |  |  | 6.6 | ns | Within pulse width distortion (PWD) limit | 3 |
| Data Rate |  | 150 |  |  | Mbps | Within PWD limit | 3 |
| Propagation Delay | tPHL, tPLH | 4.8 | 7.2 | 13 | ns | 50% input to 50% output | 3 |
| Pulse Width Distortion | PWD |  | 0.5 | 3 | ns | /tPLH − tPHL/ | 3 |
| Change vs. Temperature |  |  | 1.5 |  | ps/°C |  | 3 |
| Propagation Delay Skew | tPSK |  |  | 6.1 | ns | Between any two units at the same temperature, voltage, and load | 3 |
| Channel Matching Codirectional | tPSKCD |  | 0.5 | 3 | ns |  | 3 |
| Channel Matching Opposing Direction | tPSKOD |  | 0.5 | 3 | ns |  | 3 |
| Output Voltage Logic Low | VOL | 0 |  | 0.1 | V | IOx = 20 µA, VIx = VIxL | 4 |
| Output Voltage Logic Low | VOL | 0 |  | 0.4 | V | IOx = 4 mA, VIx = VIxL | 4 |
| UVLO Positive Going Threshold | VUV+ |  | 1.6 |  | V | VDD1, VDD2, and VDDP supply | 4 |
| UVLO Negative Going Threshold | VUV− |  | 1.5 |  | V | VDD1, VDD2, and VDDP supply | 4 |
| UVLO Hysteresis | VUVH |  | 0.1 |  | V | VDD1, VDD2, and VDDP supply | 4 |
| Input Currents per Channel | II | -10 | 0.01 | 10 | µA | 0 V ≤ VIx ≤ VDDx | 4 |
| ADuM5410 Quiescent IDD1, logic 0 | IDD1 (Q) |  | 1.2 | 2.2 | mA | VIx = Logic 0 | 4 |
| ADuM5410 Quiescent IDD2, logic 0 | IDD2 (Q) |  | 2 | 2.72 | mA | VIx = Logic 0 | 4 |
| ADuM5410 Quiescent IDD1, logic 1 | IDD1 (Q) |  | 12 | 20 | mA | VIx = Logic 1 | 4 |
| ADuM5410 Quiescent IDD2, logic 1 | IDD2 (Q) |  | 2 | 2.92 | mA | VIx = Logic 1 | 4 |
| Dynamic Supply Current, Input | IDDI (D) |  | 0.01 |  | mA/Mbps | Inputs switching, 50% duty cycle | 4 |
| Dynamic Supply Current, Output | IDDO (D) |  | 0.01 |  | mA/Mbps | Inputs switching, 50% duty cycle | 4 |
| Output Rise/Fall Time | tR/tF |  | 2.5 |  | ns | 10% to 90% | 4 |
| Common-Mode Transient Immunity (high) | /CMH/ | 75 | 100 |  | kV/µs | VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V | 4 |
| Common-Mode Transient Immunity (low) | /CML/ | 75 | 100 |  | kV/µs | VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V | 4 |
| Input-Output Capacitance | CI-O |  | 2.2 |  | pF | f = 1 MHz | 12 |
| Input Capacitance | CI |  | 4 |  | pF |  | 12 |
| Junction to Ambient Thermal Resistance | θJA |  | 50 |  | °C/W | Thermocouple at center of package underside, 4-layer board with thin traces | 12 |
| Operating Temperature | TA | -40 |  | 105 | °C |  | 14 |
| VDDP supply at VISO = 3.0 V to 3.6 V | VDDP | 3 |  | 5.5 | V | VISO = 3.0 V to 3.6 V | 14 |
| VDDP supply at VISO = 4.5 V to 5.5 V | VDDP | 4.5 |  | 5.5 | V | VISO = 4.5 V to 5.5 V | 14 |
| VDD1, VDD2 supply | VDD1, VDD2 | 1.7 |  | 5.5 | V |  | 15 |
| Storage Temperature | TST | -55 |  | 150 | °C |  | 16 |
| Ambient Operating Temperature | TA | -40 |  | 105 | °C |  | 16 |
| Supply Voltages | VDD1, VDDP, VDD2, VISO | -0.5 |  | 7 | V | Relative to respective ground | 16 |
| VISO Supply Current |  |  |  | 30 | mA | TA = −40°C to +105°C | 16 |
| Input Voltage |  | -0.5 |  |  | V | VIA, VIB, VIC, VID, VE1, VE2, VSEL, PDIS; max VDDI + 0.5 V | 16 |
| Output Voltage |  | -0.5 |  |  | V | VOA, VOB, VOC, VOD; max VDDO + 0.5 V | 16 |
| Average Output Current Per Data Output Pin |  | -10 |  | 10 | mA |  | 16 |
| Common-Mode Transients |  | -150 |  | 150 | kV/µs |  | 16 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC |  | In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM5410/ADuM5411/ADuM5412 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limi | 13 |

## CAD (KiCad official)

- Symbol: `ADUM5410BRSZ`
- Footprint: `Package_SO:SSOP-24_5.3x8.2mm_P0.65mm`
- 3D model: SSOP-24 (KiCad packages3D, STEP)
- 3D model files: `adum5410brsz-etched.step` / `adum5410brsz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adum5410brsz.step` / `adum5410brsz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM5410-5411-5412.pdf) (30 pp, sha256 `5762eced48c3a69d`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/adum5410brsz-datasheet.pdf)