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ADUM5402WCRWZ-1

Analog Devices · Digital Isolators · SOIC-16

ADUM5402WCRWZ-1 from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Primary supply voltage, 3.0 V to 5.5 V.
2	GND1	power_in	Ground reference for the primary side of the isolator; pin 2 and pin 8 are internally connected and both should be connected to a common ground.
3	VIA	input	Logic Input A.
4	VIB	input	Logic Input B.
5	VOC	output	Logic Output C.
6	VOD	output	Logic Output D.
7	RCOUT	output	Regulation control output that connects to the RCIN pin of a slave isoPower device to control its regulation; it is a nonstandard output not recommended for standard digital loads.
8	GND1	power_in	Ground reference for the primary side of the isolator; internally connected to pin 2 and should be connected to a common ground.
9	GNDISO	power_in	Ground reference for the secondary side of the isolator; pin 9 and pin 15 are internally connected and both should be connected to a common ground.
10	VSEL	input	Output voltage selection: VISO setpoint is 5.0 V when VSEL = VISO and 3.3 V when VSEL = GNDISO.
11	VID	input	Logic Input D.
12	VIC	input	Logic Input C.
13	VOB	output	Logic Output B.
14	VOA	output	Logic Output A.
15	GNDISO	power_in	Ground reference for the secondary side of the isolator; internally connected to pin 9 and should be connected to a common ground.
16	VISO	power_out	Secondary supply voltage output for external loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-16
Category	Signal Isolation Devices
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Setpoint	VISO	4.7	5	5.4	V	IISO = 0 mA	4
Load Regulation	VISO (LOAD)		1	5	%	IISO = 10 mA to 90 mA	4
IDD1, No VISO Load	IDD1 (Q)		20	35	mA		4
Propagation Delay	tPHL, tPLH		45	60	ns	50% input to 50% output	4
Input Currents Per Channel	II	-20	0.01	20	µA	0 V ≤ VIx ≤ VDD1 or VISO	5
Common-Mode Transient Immunity	/CM/	25	35		kV/µs	VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V	5
Setpoint	VISO	3	3.3	3.6	V	IISO = 0 mA	6
Load Regulation	VISO (LOAD)		1	5	%	IISO = 6 mA to 54 mA	6
IDD1, No VISO Load	IDD1 (Q)		14	22	mA		6
Propagation Delay	tPHL, tPLH		45	60	ns	50% input to 50% output	7
Input Currents per Channel	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDD1 or VISO	7
Common-Mode Transient Immunity	/CM/	25	35		kV/µs	VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V	7
Setpoint	VISO	3	3.3	3.6	V	IISO = 0 mA	8
Load Regulation	VISO (LOAD)		1	5	%	IISO = 6 mA to 54 mA	8
IDD1, No VISO Load	IDD1 (Q)		14	22	mA		8
Propagation Delay	tPHL, tPLH		45	60	ns	50% input to 50% output	8
Input Currents per Channel	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDD1 or VISO	9
Common-Mode Transient Immunity	/CM/	25	35		kV/µs	VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V	9
Operating Temperature	TA	-40		105	°C		11
Supply Voltages	VDD1	3		5.5	V		11
Storage Temperature	TST	-55		150	°C		12
Ambient Operating Temperature Range	TA	-40		105	°C		12
Supply Voltages	VDD1, VISO	-0.5		7	V	Relative to their respective grounds	12
VISO Supply Current				100	mA	TA = −40°C to +85°C	12
VISO Supply Current				60	mA	TA = −40°C to +105°C	12
Common-Mode Transients		-100		100	kV/µs	Refers to common-mode transients across the insulation barrier	12
Average Output Current Per Data Output Pin		-10		10	mA		12
IC Junction to Ambient Thermal Resistance	θJA		45		°C/W	Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces	10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pC		leakage detection limit = 10 µA). 2 In accordance with DIN EN 69747-5-2 (VDE 0884 Teil 2):2003-1, each ADuM5401W/ADuM5402W/ADuM5403W is proof tested by applying an insulation test voltage ≥ 1590 V pea	10

CAD (KiCad official)

Symbol: ADUM5402WCRWZ-1
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: adum5402wcrwz-1-etched.step / adum5402wcrwz-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum5402wcrwz-1.step / adum5402wcrwz-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (25 pp, sha256 b0c2926ec3c19a0e, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF