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ADUM5241ARZ-RL7
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Analog Devices Digital Isolators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownADUM5241ARZ-RL7
Analog Devices · Digital Isolators · SOP-8
ADUM5241ARZ-RL7 from Analog Devices, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply voltage for the isolator primary side, 4.5 V to 5.5 V with the DC-to-DC converter enabled and 2.7 V to 4.0 V with the DC-to-DC converter disabled. |
| 2 | VOA | output | Logic Output A; the datasheet specifies its logic-high level as (VDD or VISO) minus 0.1 V to 0.5 V at IOx = −20 µA to −4 mA and its logic-low level as 0.1 V typical at 20 µA and 0.4 V maximum at 4 mA. |
| 3 | VIB | input | Logic Input B; the logic-high threshold is at least 0.7 × (VDD or VISO) and the logic-low threshold is at most 0.3 × (VDD or VISO), with input current limited to ±10 µA. |
| 4 | GND | power_in | Ground reference for the isolator primary side; the datasheet recommends enlarged pads with multiple vias to the ground plane to conduct heat away from the device. |
| 5 | GNDISO | power_in | Isolated ground, the ground reference for the isolator secondary side. |
| 6 | VOB | output | Logic Output B; the datasheet specifies its logic-high level as (VDD or VISO) minus 0.1 V to 0.5 V at IOx = −20 µA to −4 mA and its logic-low level as 0.1 V typical at 20 µA and 0.4 V maximum at 4 mA. |
| 7 | VIA | input | Logic Input A; the logic-high threshold is at least 0.7 × (VDD or VISO) and the logic-low threshold is at most 0.3 × (VDD or VISO), with input current limited to ±10 µA. |
| 8 | VISO | power_out | Isolated supply voltage for the isolator secondary side, 4.5 V to 5.5 V output when the DC-to-DC converter is enabled and 2.7 V to 5.5 V input when it is disabled. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOP-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Setpoint VISO (SET) | VISO (SET) | 4.5 | 5.2 | 5.5 | V | IISO = 0 mA | 3 |
| Maximum VISO Output Current | IISO (max) | 10 | mA | VISO = 4.5 V | 3 | ||
| Noise | 250 | mV p-p | 3 | ||||
| Input Supply Current at Maximum IISO | IDD (max) | 140 | mA | IISO = 10 mA | 3 | ||
| Input Supply Current No Load | IDD (Q) | 104 | mA | IISO = 0 mA | 3 | ||
| Primary Side Supply Input Current, DC-to-DC Disabled (ADuM5241) | IDD (DISABLE) | 2.7 | mA | VDD = 4.0 V | 3 | ||
| Secondary Side Supply Input Current, DC-to-DC Disabled (ADuM5241) | IISO (DISABLE) | 2.8 | mA | 3 | |||
| DC-to-DC Converter Enable Threshold | VDD (ENABLE) | 4.2 | 4.5 | V | 3 | ||
| DC-to-DC Converter Disable Threshold | VDD (DISABLE) | 3.7 | V | 3 | |||
| Logic Input Currents | IIA, IIB | -10 | 0.01 | 10 | µA | 3 | |
| Logic Low Output Voltage (20 µA) | VOAL, VOBL | 0 | 0.1 | V | IOx = 20 µA, VIx ≤ VIL | 3 | |
| Logic Low Output Voltage (4 mA) | VOAL, VOBL | 0 | 0.4 | V | IOx = 4 mA, VIx ≤ VIL | 3 | |
| Minimum Pulse Width | PW | 100 | ns | CL = 15 pF, CMOS signal levels | 3 | ||
| Maximum Data Rate | 1 | Mbps | CL = 15 pF, CMOS signal levels | 3 | |||
| Propagation Delay | tPHL, tPLH | 25 | 70 | ns | CL = 15 pF, CMOS signal levels | 3 | |
| Pulse Width Distortion | PWD | 3 | ns | CL = 15 pF, CMOS signal levels | 3 | ||
| Propagation Delay Skew | tPSK | 45 | ns | CL = 15 pF, CMOS signal levels | 3 | ||
| Channel-to-Channel Matching, Codirectional Channels | tPSKCD | 3 | ns | CL = 15 pF, CMOS signal levels | 3 | ||
| Channel-to-Channel Matching, Opposing-Directional Channels | tPSKCD | 15 | ns | CL = 15 pF, CMOS signal levels | 3 | ||
| Output Rise/Fall Time (10% to 90%) | tR/tF | 2.5 | ns | CL = 15 pF, CMOS signal levels | 3 | ||
| Common-Mode Transient Immunity at Logic High Output | /CMH/ | 25 | 35 | kV/µs | VIx = VDD, VISO, VCM = 1000 V, transient magnitude = 800 V | 4 | |
| Common-Mode Transient Immunity at Logic Low Output | /CML/ | 25 | 35 | kV/µs | VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V | 4 | |
| IC Junction-to-Air Thermal Resistance | θJA | 80 | °C/W | 4 | |||
| Operating Temperature Range (TA) | TA | -40 | 105 | °C | 6 | ||
| Supply Voltage VDD, DC-to-DC Converter Enabled | VDD | 4.5 | 5.5 | V | DC-to-DC Converter Enabled | 6 | |
| Supply Voltage VDD, DC-to-DC Converter Disabled | VDD (DISABLE) | 2.7 | 4 | V | DC-to-DC Converter Disabled | 6 | |
| Supply Voltage VISO, DC-to-DC Converter Disabled | VISO (DISABLE) | 2.7 | 5.5 | V | DC-to-DC Converter Disabled | 6 | |
| Input Signal Rise/Fall Time | 1 | ms | 6 | ||||
| Input Supply Slew Rate | 10 | V/ms | 6 | ||||
| Storage Temperature Range | TST | -55 | 150 | °C | 7 | ||
| Ambient Operating Temperature Range | TA | -40 | 105 | °C | 7 | ||
| Supply Voltages | VDD, VISO | -0.5 | 7 | V | Relative to their respective ground | 7 | |
| Input Voltage | VIA, VIB | -0.5 | V | Relative to ground; upper limit is (VDD or VISO) + 0.5 V | 7 | ||
| Output Voltage | VOA, VOB | -0.5 | V | Relative to ground; upper limit is (VDD or VISO) + 0.5 V | 7 | ||
| Average Output Current per Pin | IO | -18 | 18 | mA | See Figure 4 for derating vs. temperature | 7 | |
| Common-Mode Transients | /CM/ | -100 | 100 | kV/µs | Across the insulation barrier | 7 | |
| Safety-Limiting Case Temperature | TS | 150 | °C | Maximum value allowed in the event of a failure | 5 | ||
| Safety-Limiting Supply Current | IS1 | 312 | mA | Maximum value allowed in the event of a failure | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM524x is proof-tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The aster | 4 |
CAD (KiCad official)
- Symbol:
ADUM5241ARZ-RL7 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
adum5241arz-rl7-etched.step/adum5241arz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum5241arz-rl7.step/adum5241arz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (17 pp, sha256
d407b0be792354b5, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).