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ADUM4165BRIZ

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Analog Devices Isolated USB ICs, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsignal isolation devicesadum4165brizfactory-2.0.0extractor-text

Verified ADUM4165BRIZ

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADUM4165BRIZ · SOIC-20-300mil · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 27-page datasheet
  • ✓distributor: lcsc C5555215, digikey 505-ADUM4165BRIZ-ND, mouser 584-ADUM4165BRIZ
  • ✓family: SOIC-20W_7.5x12.8mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-t6s86yps/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ adum4165briz.kicad_sym✓ adum4165briz.kicad_mod✓ adum4165briz.step
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Ray Publish 0.1.0 9ae5350 14h ago

ADUM4165BRIZ

Analog Devices · Isolated USB ICs · SOIC-20-300mil

ADUM4165BRIZ from Analog Devices, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBUS1 power_in Optional 5 V power supply/LDO input for Side 1, to be connected to 4.5 V to 5.5 V and bypassed to GND1 with 0.1 μF.
2 GND1 power_in Ground reference for Isolator Side 1, to be connected to the Side 1 PCB ground.
3 VDD1 power_out 3.3 V LDO output for Side 1, requiring a 0.1 μF bypass to GND1 for correct operation of the internal regulator.
4 GND1 power_in Side 1 ground pin that must be connected to Side 1 PCB ground and is not suitable for bypass capacitance.
5 XI1 input Crystal input or external clock input for Isolator Side 1.
6 XO1 output Crystal output driver for Isolator Side 1, left open when an external clock is applied to XI1.
7 GND1 power_in Side 1 ground pin that must be connected to Side 1 PCB ground and is not suitable for bypass capacitance.
8 UD+ bidirectional USB D+ signal, upstream (Isolator Side 1).
9 UD− bidirectional USB D− signal, upstream (Isolator Side 1).
10 GND1 power_in Ground reference for Isolator Side 1, to be connected to the Side 1 PCB ground.
11 GND2 power_in Ground reference for Isolator Side 2, to be connected to the Side 2 PCB ground.
12 DD+ bidirectional USB D+ signal, downstream (Isolator Side 2).
13 DD− bidirectional USB D− signal, downstream (Isolator Side 2).
14 PGOOD output Power Good output, high when VBUS1/VDD1 and VBUS2/VDD2 are above UVLO thresholds and low when either is below; low forces Side 2 into low power standby mode.
15 GND2 power_in Side 2 ground pin that must be connected to Side 2 PCB ground and is not suitable for bypass capacitance.
16 GND2 power_in Side 2 ground pin that must be connected to Side 2 PCB ground and is not suitable for bypass capacitance.
17 GND2 power_in Side 2 ground pin that must be connected to Side 2 PCB ground and is not suitable for bypass capacitance.
18 VDD2 power_out 3.3 V LDO output for Side 2, requiring a 0.1 μF bypass to GND2 for correct operation of the internal regulator.
19 GND2 power_in Ground reference for Isolator Side 2, to be connected to the Side 2 PCB ground.
20 VBUS2 power_in Optional 5 V power supply/LDO input for Side 2, to be connected to 4.5 V to 5.5 V and bypassed to GND2 with 0.1 μF.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-20-300mil
Category Signal Isolation Devices
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply current idle low or full speed mode IDD1(LFI) 21 27 mA UD+, UD−, DD+, and DD− idle 3
Supply current idle high speed mode IDD1(HI) 48 60 mA UD+, UD−, DD+, and DD− idle 3
Supply current busy low speed mode IDD1(L) 29 45 mA fIN = 750 kHz, CL = 450 pF 3
Supply current busy full speed mode IDD1(F) 31 45 mA fIN = 6 MHz, CL = 50 pF 3
Supply current busy high speed mode IDD1(H) 59 70 mA fIN = 240 MHz, CL = 10 pF 3
Low power standby supply current upstream IDD1(S) 1.7 2.5 mA Side 2 not powered 3
Low power standby supply current downstream IDD2(S) 20 40 µA VBUS2 = VDD2 = 3 V to 3.6 V, Side 1 not powered 3
Low power standby supply current downstream IDD2(S) 40 100 µA VBUS2 = 4.5 V to 5.5 V, Side 1 not powered 3
VDD2 maximum voltage until after side 1 start-up VSTART 3.5 V See the PGOOD, Clock, and Power Sequencing section 3
Side 1 start-up time tSTART 3 ms Time after VDD1 rises above VUVLO3+ before VDD2 can be >3.5 V 3
UVLO threshold VBUS1 or VBUS2 rising VUVLO5+ 3.5 4.16 4.35 V 3
UVLO threshold VBUS1 or VBUS2 falling VUVLO5− 3 3.77 3.95 V 3
VBUS1 or VBUS2 UVLO hysteresis VUVLO5HST 0.44 V 3
UVLO threshold VDD1 or VDD2 rising VUVLO3+ 2.4 2.77 2.95 V 3
UVLO threshold VDD1 or VDD2 falling VUVLO3− 2.2 2.6 2.9 V 3
VDD1 or VDD2 UVLO hysteresis VUVLO3HST 0.18 V 3
Input current UD+ and UD− IIN -20 0.1 20 µA 0 V ≤ VIN ≤ 3.6 V 3
Input current DD+ and DD− IIN -250 0.1 250 µA 0 V ≤ VIN ≤ 3.6 V 3
Input current XI1 and XI2 IIN -30 0.1 30 µA 0 V ≤ VIN ≤ 3.6 V 3
Input logic high threshold VIH 2 V Single-ended inputs 3
Input logic low threshold VIL 0.8 V Single-ended inputs 3
Input hysteresis VHYS 0.4 V Single-ended inputs 3
Propagation delay low speed tPHLL, tPLHL 300 500 600 ns CL = 450 pF, TA = 25°C and VDD1 = VDD2 = 3.3 V 5
Propagation delay low speed tPHLL, tPLHL 300 500 650 ns CL = 450 pF 5
Output rise and fall time low speed (10% to 90%) tRL/tFL 75 300 ns CL = 450 pF, TA = 25°C and VDD1 = VDD2 = 3.3 V 5
Output rise and fall time low speed (10% to 90%) tRL/tFL 75 350 ns CL = 450 pF 5
Differential jitter next transition low speed /tLJN/ 5 ns CL = 450 pF 5
Differential jitter paired J to K transition low speed /tLJPJK/ 2 ns CL = 450 pF 5
Differential jitter paired K to J transition low speed /tLJPKJ/ 3 ns CL = 450 pF 5
Propagation delay full speed tPHLF, tPLHF 70 110 140 ns CL = 50 pF 5
Output rise/fall time full speed (10% to 90%) tRF/tFF 4 20 ns TA = 25°C and VDD1 = VDD2 = 3.3 V 5
Output rise/fall time full speed (10% to 90%) tRF/tFF 4 32 ns 5
Differential jitter next transition full speed /tFJN/ 450 ps CL = 50 pF 5
Differential jitter paired J to K transition full speed /tFJPJK/ 300 ps CL = 50 pF 5
Differential jitter paired K to J transition full speed /tFJPKJ/ 500 ps CL = 50 pF 5
Propagation delay high speed tPHLH, tPLHH 71 73 77 ns CL = 10 pF 5
Output rise and fall time high speed (10% to 90%) tRH, tFH 675 ps CL = 10 pF 5
Differential jitter rms next transition high speed /tHJN(R)/ 40 ps rms CL = 10 pF 5
Differential jitter rms paired J to K transition high speed /tHJPJK(R)/ 11 ps rms CL = 10 pF 5
Differential jitter rms paired K to J transition high speed /tHJPKJ(R)/ 14 ps rms CL = 10 pF 5
Differential jitter peak next transition high speed /tHJN(P)/ 90 ps CL = 10 pF 5
Differential jitter peak paired J to K transition high speed /tHJPJK(P)/ 30 ps CL = 10 pF 5
Differential jitter peak paired K to J transition high speed /tHJPKJ(P)/ 40 ps CL = 10 pF 5
Operating temperature range TA -55 125 °C 9
Supply voltage VBUS1, VBUS2 VBUS1, VBUS2 3 5.5 V 9
Supply voltage VDD1, VDD2 VDD1, VDD2 3 3.6 V 9
Supply (VBUS1, VDD1) to GND1 -0.5 6.5 V 10
Supply (VBUS2, VDD2) to GND2 -0.5 6.5 V 10
Common-mode transients -100 100 kV/µs Across the insulation barrier 10
Operating temperature range -55 125 °C 10
Storage temperature range -65 150 °C 10
Maximum junction temperature TJ 150 °C 10
Thermal resistance junction to ambient θJA 50 °C/W Package RI-20-1, 4-layer standard JEDEC PCB 10
Junction to top thermal characterization parameter ΨJT 2.3 °C/W Package RI-20-1, 4-layer standard JEDEC PCB 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM4165/ADuM4166 is proof tested by applying an insulation test voltage ≥1592 V peak for 1 sec (partial discharge detection limit = 5 pC). 7

CAD (KiCad official)

  • Symbol: ADUM4165BRIZ
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: adum4165briz-etched.step / adum4165briz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum4165briz.step / adum4165briz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (27 pp, sha256 d6eedaec07325ba9, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF