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ADUM4152BRIZ-RL

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Analog Devices Digital Isolators, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADUM4152BRIZ-RL

Analog Devices · Digital Isolators · SOIC-20-300mil

ADUM4152BRIZ-RL from Analog Devices, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Power supply for isolator side 1; a bypass capacitor from VDD1 to GND1 to local ground is required.
2 GND1 power_in Ground reference for isolator side 1.
3 MCLK input SPI clock input from the main controller.
4 MO input SPI data input from the main to the subordinate (MO/SI line).
5 MI output SPI data output from the subordinate to the main (MI/SO line).
6 MSS input Active-low subordinate select input from the main; requires a 10 ns setup time from the next clock or data edge.
7 VIA input Low-speed data input A.
8 VOB output Low-speed data output B.
9 VOC output Low-speed data output C.
10 GND1 power_in Ground reference for isolator side 1.
11 GND2 power_in Ground reference for isolator side 2.
12 VIC input Low-speed data input C.
13 VIB input Low-speed data input B.
14 VOA output Low-speed data output A.
15 SSS output Active-low subordinate select output to the subordinate.
16 SO input SPI data input from the subordinate to the main (MI/SO line).
17 SI output SPI data output from the main to the subordinate (MO/SI line).
18 SCLK output SPI clock output from the main controller.
19 GND2 power_in Ground reference for isolator side 2.
20 VDD2 power_in Power supply for isolator side 2; a bypass capacitor from VDD2 to GND2 to local ground is required.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-20-300mil
Category Communication Interface Chip/UART/485/232
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
SPI Clock Rate (B grade) SPIMCLK 17 MHz 3
Data Rate Fast MO/SO, 5 V (B grade) DRFAST 34 Mbps Within PWD limit 3
Propagation Delay MO/SO/MCLK, 5 V (B grade) tPHL, tPLH 12 14 ns 50% input to 50% output 3
Pulse Width MCLK/MO/SO, 5 V (B grade) PW 12.5 ns Within PWD limit 3
Pulse Width Distortion MCLK/MO/SO, 5 V (B grade) PWD 2 ns /tPLH − tPHL/ 3
Codirectional Channel Matching, 5 V (B grade) tPSKCD 2 ns 3
Jitter High Speed MCLK/MO/SO, 5 V (B grade) JHS 1 ns 3
Data Rate Fast MSS, 5 V (B grade) DRFAST 34 Mbps Within PWD limit 3
Propagation Delay MSS, 5 V (B grade) tPHL, tPLH 21 25 ns 50% input to 50% output 3
Pulse Width MSS, 5 V (B grade) PW 12.5 ns Within PWD limit 3
Pulse Width Distortion MSS, 5 V (B grade) PWD 3 ns /tPLH − tPHL/ 3
MSS Setup Time, 5 V (B grade) MSSSETUP 10 ns 3
Jitter High Speed MSS, 5 V (B grade) JHS 1 ns 3
Propagation Delay VIA/VIB/VIC, 5 V tPHL, tPLH 0.1 2.6 µs 50% input to 50% output 3
Pulse Width VIA/VIB/VIC, 5 V PW 4 µs Within PWD limit 3
Jitter Low Speed VIA/VIB/VIC, 5 V JLS 2.5 µs 3
VIx Minimum Input Skew, 5 V tVIx SKEW 10 ns 3
Supply Current IDD1 ADuM4152, 5 V (17 MHz, B grade) IDD1 21.5 mA CL = 0 pF, low speed channels 3
Supply Current IDD2 ADuM4152, 5 V (17 MHz, B grade) IDD2 22.5 mA CL = 0 pF, low speed channels 3
Input Current per Channel II -1 0.01 1 µA 0 V ≤ VINPUT ≤ VDDx 4
Logic Low Output Voltage (low-current) VOL 0.1 V IOUTPUT = 20 µA, VINPUT = VIL 4
Logic Low Output Voltage (4 mA) VOL 0.4 V IOUTPUT = 4 mA, VINPUT = VIL 4
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% 4
Common-Mode Transient Immunity /CM/ 25 35 kV/µs VINPUT = VDDx, VCM = 1000 V, transient magnitude = 800 V 4
Propagation Delay MCLK/MO/SO, 3.3 V (B grade) tPHL, tPLH 20 ns 50% input to 50% output 4
SPI Clock Rate, 3.3 V (B grade) SPIMCLK 12.5 MHz 4
Data Rate Fast MO/SO, 3.3 V (B grade) DRFAST 34 Mbps Within PWD limit 4
Pulse Width MCLK/MO/SO, 3.3 V (B grade) PW 12.5 ns Within PWD limit 4
Pulse Width Distortion MCLK/MO/SO, 3.3 V (B grade) PWD 3 ns /tPLH − tPHL/ 4
Codirectional Channel Matching, 3.3 V (B grade) tPSKCD 2 ns 4
Jitter High Speed MCLK/MO/SO, 3.3 V (B grade) JHS 1 ns 4
Data Rate Fast MSS, 3.3 V (B grade) DRFAST 34 Mbps Within PWD limit 4
Propagation Delay MSS, 3.3 V (B grade) tPHL, tPLH 30 ns 50% input to 50% output 4
Pulse Width MSS, 3.3 V (B grade) PW 12.5 ns Within PWD limit 5
Pulse Width Distortion MSS, 3.3 V (B grade) PWD 3 ns /tPLH − tPHL/ 5
MSS Setup Time, 3.3 V (B grade) MSSSETUP 10 ns 5
Jitter Low Speed MSS section, 3.3 V (B grade) JLS 2.5 ns 5
Propagation Delay VIA/VIB/VIC, 3.3 V tPHL, tPLH 0.1 2.6 µs 50% input to 50% output 5
Pulse Width VIA/VIB/VIC, 3.3 V PW 4 µs Within PWD limit 5
Jitter Low Speed VIA/VIB/VIC, 3.3 V JLS 2.5 µs 5
VIx Minimum Input Skew, 3.3 V tVIx SKEW 10 ns 5
Supply Current IDD1 ADuM4152, 3.3 V (17 MHz, B grade) IDD1 18 mA CL = 0 pF, low speed channels 5
Supply Current IDD2 ADuM4152, 3.3 V (17 MHz, B grade) IDD2 16 mA CL = 0 pF, low speed channels 5
Supply Current IDD1 ADuM4152, mixed 5 V/3.3 V (17 MHz, B grade) IDD1 21.5 mA CL = 0 pF, low speed channels 7
Supply Current IDD2 ADuM4152, mixed 5 V/3.3 V (17 MHz, B grade) IDD2 16 mA CL = 0 pF, low speed channels 7
Supply Current IDD1 ADuM4152, mixed 3.3 V/5 V (17 MHz, B grade) IDD1 18 mA CL = 0 pF, low speed channels 8
Supply Current IDD2 ADuM4152, mixed 3.3 V/5 V (17 MHz, B grade) IDD2 22.5 mA CL = 0 pF, low speed channels 8
Storage Temperature Range TST -65 150 °C 12
Ambient Operating Temperature Range TA -40 125 °C 12
Supply Voltages VDD1, VDD2 -0.5 7 V 12
Average Current per Output Pin -10 10 mA 12
Common-Mode Transients -100 100 kV/µs 12
Operating Temperature Range TA -40 125 °C 11
Supply Voltage Range VDD1, VDD2 3 5.5 V 11
Input Signal Rise and Fall Times 1 ms 11
IC Junction to Ambient Thermal Resistance θJA 46 °C/W Thermocouple located at center of package underside 9
Quiescent Side 1 Current, 5 V IDD1(Q) 4.3 mA 4
Quiescent Side 2 Current, 5 V IDD2(Q) 6.1 mA 4
Quiescent Side 1 Current, 3.3 V IDD1(Q) 2.9 mA 5
Quiescent Side 2 Current, 3.3 V IDD2(Q) 4.7 mA 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each model is proof tested by applying an insulation test voltage ≥ 1209 V peak for 1 second (partial discharge detection limit = 5 pC). 9

CAD (KiCad official)

  • Symbol: ADUM4152BRIZ-RL
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: adum4152briz-rl-etched.step / adum4152briz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum4152briz-rl.step / adum4152briz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (21 pp, sha256 c05a7cc43acbf6c3, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF