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ADUM4151BRIZ

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Analog Devices Pre-ordered Chips, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified ADUM4151BRIZ

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADUM4151BRIZ · SOIC-20-300mil · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 21-page datasheet
  • ✓distributor: lcsc C660954, digikey 505-ADUM4151BRIZ-ND, mouser 584-ADUM4151BRIZ
  • ✓family: SOIC-20W_7.5x12.8mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-fjd5hwcp/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ adum4151briz.kicad_sym✓ adum4151briz.kicad_mod✓ adum4151briz.step
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Ray Publish 0.1.0 90c45df 4d ago

ADUM4151BRIZ

Analog Devices · Pre-ordered Chips · SOIC-20-300mil

ADUM4151BRIZ from Analog Devices, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Power supply for isolator side 1; a bypass capacitor from VDD1 to GND1 is required.
2 GND1 power_in Ground 1, ground reference for isolator side 1.
3 MCLK input SPI clock input from the main controller.
4 MO input SPI data input from the main to the subordinate on the MO/SI line.
5 MI output SPI data output from the subordinate to the main on the MI/SO line.
6 MSS input Active-low subordinate select input from the main; requires a 10 ns setup time from the next clock or data edge.
7 VIA input Low speed data input A.
8 VIB input Low speed data input B.
9 VOC output Low speed data output C.
10 GND1 power_in Ground 1, ground reference for isolator side 1.
11 GND2 power_in Ground 2, ground reference for isolator side 2.
12 VIC input Low speed data input C.
13 VOB output Low speed data output B.
14 VOA output Low speed data output A.
15 SSS output Active-low subordinate select output to the subordinate.
16 SO input SPI data input from the subordinate on the MI/SO line.
17 SI output SPI data output from the main to the subordinate on the MO/SI line.
18 SCLK output SPI clock output to the subordinate.
19 GND2 power_in Ground 2, ground reference for isolator side 2.
20 VDD2 power_in Power supply for isolator side 2; a bypass capacitor from VDD2 to GND2 is required.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-20-300mil
Category Interface ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature Range TA -40 125 °C 11
Supply Voltage Range VDD1, VDD2 3 5.5 V 11
Input Signal Rise and Fall Times 1 ms 11
Storage Temperature Range TST -65 150 °C TA = 25°C 12
Ambient Operating Temperature Range TA -40 125 °C TA = 25°C 12
Supply Voltages VDD1, VDD2 -0.5 7 V TA = 25°C 12
Input Voltages (lower limit; upper is VDDx + 0.5 V) -0.5 V VIA, VIB, VIC, MCLK, MO, SO, MSS; upper limit VDDx + 0.5 V 12
Average Current per Output Pin -10 10 mA 12
Common-Mode Transients -100 100 kV/µs across the insulation barrier 12
IC Junction to Ambient Thermal Resistance θJA 46 °C/W Thermocouple located at center of package underside 9
SPI Clock Rate (MCLK, MO, SO) SPIMCLK 17 MHz 5 V operation, B grade 3
Data Rate Fast (MO, SO) DRFAST 34 Mbps Within PWD limit; 5 V, B grade 3
Propagation Delay (MCLK, MO, SO) tPHL, tPLH 12 14 ns 50% input to 50% output; 5 V, B grade 3
Pulse Width (MCLK, MO, SO) PW 12.5 ns Within PWD limit; 5 V, B grade 3
Pulse Width Distortion (MCLK, MO, SO) PWD 2 ns /tPLH − tPHL/; 5 V, B grade 3
Codirectional Channel Matching tPSKCD 2 ns 5 V, B grade 3
Jitter, High Speed (MCLK, MO, SO) JHS 1 ns 5 V, B grade 3
Data Rate Fast (MSS) DRFAST 34 Mbps Within PWD limit; 5 V 3
Propagation Delay (MSS) tPHL, tPLH 21 25 ns 50% input to 50% output; 5 V, B grade 3
Pulse Width (MSS) PW 12.5 ns Within PWD limit; 5 V, B grade 3
Pulse Width Distortion (MSS) PWD 3 ns /tPLH − tPHL/; 5 V, B grade 3
Setup Time (MSS) MSSSETUP 10 ns 5 V, B grade 3
Jitter, High Speed (MSS) JHS 1 ns 5 V, B grade 3
Data Rate Slow (VIA, VIB, VIC) DRSLOW 250 kbps Within PWD limit; 5 V 3
Propagation Delay (VIA, VIB, VIC) tPHL, tPLH 0.1 2.6 µs 50% input to 50% output; 5 V 3
Pulse Width (VIA, VIB, VIC) PW 4 µs Within PWD limit; 5 V 3
Jitter, Low Speed JLS 2.5 µs 5 V 3
VIx Minimum Input Skew tVIx SKEW 10 ns 5 V 3
SPI Clock Rate (MCLK, MO, SO) SPIMCLK 12.5 MHz 3.3 V operation, B grade 4
Propagation Delay (MCLK, MO, SO) tPHL, tPLH 20 ns 50% input to 50% output; 3.3 V, B grade 4
Supply Current Side 1 (ADuM4151) IDD1 14 22 mA 17 MHz, B grade; CL = 0 pF, low speed channels; 5 V 3
Supply Current Side 2 (ADuM4151) IDD2 13.5 23 mA 17 MHz, B grade; CL = 0 pF, low speed channels; 5 V 3
Supply Current Side 1 (ADuM4151) IDD1 10.5 18 mA 17 MHz, B grade; CL = 0 pF, low speed channels; 3.3 V 5
Supply Current Side 2 (ADuM4151) IDD2 9 17 mA 17 MHz, B grade; CL = 0 pF, low speed channels; 3.3 V 5
Supply Current Side 1 (ADuM4151) IDD1 13.9 22 mA 17 MHz, B grade; CL = 0 pF, low speed channels; VDD1 = 5 V, VDD2 = 3.3 V 7
Supply Current Side 2 (ADuM4151) IDD2 9 17 mA 17 MHz, B grade; CL = 0 pF, low speed channels; VDD1 = 5 V, VDD2 = 3.3 V 7
Supply Current Side 1 (ADuM4151) IDD1 10.5 18 mA 17 MHz, B grade; CL = 0 pF, low speed channels; VDD1 = 3.3 V, VDD2 = 5 V 8
Supply Current Side 2 (ADuM4151) IDD2 13 23 mA 17 MHz, B grade; CL = 0 pF, low speed channels; VDD1 = 3.3 V, VDD2 = 5 V 8
Input Current per Channel II -1 0.01 1 µA 0 V ≤ VINPUT ≤ VDDx 4
Input Hysteresis VIHYST 500 mV 4
Logic High Output Voltage VOH 5 V IOUTPUT = −20 µA, VINPUT = VIH; 5 V; min is VDDx − 0.1 4
Logic High Output Voltage VOH 4.8 V IOUTPUT = −4 mA, VINPUT = VIH; 5 V; min is VDDx − 0.4 4
Logic Low Output Voltage VOL 0 0.1 V IOUTPUT = 20 µA, VINPUT = VIL 4
Logic Low Output Voltage VOL 0.2 0.4 V IOUTPUT = 4 mA, VINPUT = VIL 4
VDD1, VDD2 Undervoltage Lockout UVLO 2.6 V 4
Quiescent Side 1 Current IDD1(Q) 4.3 mA All low speed channels; 5 V 4
Quiescent Side 2 Current IDD2(Q) 6.1 mA All low speed channels; 5 V 4
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% 4
Common-Mode Transient Immunity /CM/ 25 35 kV/µs VINPUT = VDDx, VCM = 1000 V, transient magnitude = 800 V 4
Dynamic Input Supply Current IDDI(D) 0.08 mA/Mbps Per high speed channel; 5 V 4
Dynamic Output Supply Current IDDO(D) 0.046 mA/Mbps Per high speed channel; 5 V 4
Capacitance (Input to Output) CI-O 1 pF f = 1 MHz 9
Input Capacitance CI 4 pF From any input data pin to ground 9
Maximum Repetitive Isolation Voltage VIORM 645 V peak 10
Safety Limiting Case Temperature TS 130 °C Maximum value allowed in the event of a failure 10
Safety Total Dissipated Power PS 2.4 W Maximum value allowed in the event of a failure 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each model is proof tested by applying an insulation test voltage ≥ 1209 V peak for 1 second (partial discharge detection limit = 5 pC). 9

CAD (KiCad official)

  • Symbol: ADUM4151BRIZ
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: adum4151briz-etched.step / adum4151briz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum4151briz.step / adum4151briz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (21 pp, sha256 c05a7cc43acbf6c3, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF