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ADUM3470ARSZ

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Analog Devices Digital Isolators, SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232adum3470arszfactory-2.0.0extractor-text

Verified ADUM3470ARSZ

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADUM3470ARSZ · SSOP-20-208mil · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 34-page datasheet
  • ✓distributor: lcsc C660866, digikey ADUM3470ARSZ-ND, mouser 584-ADUM3470ARSZ
  • ✓family: SSOP-20_5.3x7.2mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qck3_bpf/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ adum3470arsz.kicad_sym✓ adum3470arsz.kicad_mod✓ adum3470arsz.step
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ADUM3470ARSZ

Analog Devices · Digital Isolators · SSOP-20-208mil

ADUM3470ARSZ from Analog Devices, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 X1 output Transformer Driver Output 1.
2 GND1 power_in Ground reference for the primary side of the isolator; internally connected to pin 10 and both should be tied to a common ground.
3 NC unconnected No internal connection.
4 X2 output Transformer Driver Output 2.
5 VIA input Logic Input A.
6 VIB input Logic Input B.
7 VIC input Logic Input C.
8 VID input Logic Input D.
9 VDDA power_in Supply voltage for the primary side, 3.0 V to 5.5 V; connect a 0.1 µF bypass capacitor from VDDA to GND1.
10 GND1 power_in Ground reference for the primary side of the isolator; internally connected to pin 2 and both should be tied to a common ground.
11 GND2 power_in Ground reference for the secondary side of the isolator; internally connected to pin 19 and both should be tied to a common ground.
12 OC input Oscillator control pin: tied to VDD2 for open-loop (unregulated) mode, or connect a resistor to GND2 to run the secondary controller at 200 kHz to 1 MHz.
13 VOD output Logic Output D.
14 VOC output Logic Output C.
15 VOB output Logic Output B.
16 VOA output Logic Output A.
17 FB input Feedback input from the secondary output voltage VISO via a resistor divider setting VFB to the 1.25 V reference (VISO = VFB × (R1 + R2)/R2); the divider is required even in open-loop mode for soft start.
18 VDD2 power_in Internal supply for the secondary side controller and Side 2 data channels; regulated to 5.0 V when VREG is sufficiently supplied, otherwise 3.0 V to 5.5 V, with a 0.1 µF bypass capacitor to GND2.
19 GND2 power_in Ground reference for the secondary side of the isolator; internally connected to pin 11 and both should be tied to a common ground.
20 VREG power_in Input of the internal regulator powering the secondary side controller and Side 2 data channels; should be 5.5 V to 15 V to regulate VDD2 to 5.0 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SSOP-20-208mil
Category Communication Interface Chip/UART/485/232
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Isolated Output Voltage VISO 4.5 5 5.5 V IISO = 0 mA, VISO = VFB × (R1 + R2)/R2 3
Feedback Voltage Setpoint VFB 1.125 1.25 1.375 V IISO = 0 mA 3
Line Regulation VISO (LINE) 1 10 mV/V IISO = 50 mA, VDD1 = 4.5 V to 5.5 V 3
Load Regulation VISO (LOAD) 1 2 % IISO = 50 mA to 200 mA 3
Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth, COUT = 0.1 µF//47 µF, IISO = 100 mA 3
Output Noise VISO (N) 100 mV p-p 20 MHz bandwidth, COUT = 0.1 µF//47 µF, IISO = 100 mA 3
Switching Frequency (open loop) fSW 192 318 515 kHz VOC = VDD2 (open loop) 3
Switch On Resistance RON 0.5 Ω 3
UVLO Positive Going Threshold VUV+ 2.8 V VDD1, VDD2 supplies 3
UVLO Negative Going Threshold VUV− 2.6 V VDD1, VDD2 supplies 3
UVLO Hysteresis VUVH 0.2 V VDD1, VDD2 supplies 3
Maximum Output Supply Current IISO (MAX) 400 mA VISO = 5.0 V 3
Efficiency at Maximum Output Supply Current 70 % IISO = IISO (MAX) 3
IDD1 Supply Current, No VISO Load (ADuM3470) IDD1 (Q) 14 30 mA IISO = 0 mA, f ≤ 1 MHz 3
IDD1 Supply Current, Full VISO Load IDD1 (MAX) 550 mA CL = 0 pF, f = 0 MHz, VDD1 = 5 V, IISO = 400 mA 4
I/O Input Currents IIA, IIB, IIC, IID -20 0.01 20 µA 4
Logic High Input Threshold VIH 2 V 4
Logic Low Input Threshold VIL 0.8 V 4
Logic High Output Voltage VOAH, VOBH, VOCH, VODH 5 V IOx = −20 µA, VIx = VIxH 4
Logic High Output Voltage VOAH, VOBH, VOCH, VODH 4.8 V IOx = −4 mA, VIx = VIxH 4
Logic Low Output Voltage VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 µA, VIx = VIxL 4
Logic Low Output Voltage VOAL, VOBL, VOCL, VODL 0 0.4 V IOx = 4 mA, VIx = VIxL 4
Minimum Pulse Width (A Grade) PW 1000 ns CL = 15 pF, CMOS signal levels 4
Maximum Data Rate (A Grade) 1 Mbps CL = 15 pF, CMOS signal levels 4
Propagation Delay (A Grade) tPHL, tPLH 55 100 ns CL = 15 pF, CMOS signal levels 4
Pulse Width Distortion (A Grade) PWD 40 ns /tPLH − tPHL/, CL = 15 pF, CMOS signal levels 4
Propagation Delay Skew (A Grade) tPSK 50 ns CL = 15 pF, CMOS signal levels 4
Channel-to-Channel Matching (A Grade) tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels 4
Common-Mode Transient Immunity, Logic High Output /CMH/ 25 35 kV/µs VIx = VDD1 or VISO; VCM = 1000 V, transient magnitude = 800 V 4
Common-Mode Transient Immunity, Logic Low Output /CML/ 25 35 kV/µs VIx = 0 V; VCM = 1000 V, transient magnitude = 800 V 4
Refresh Rate fr 1 Mbps 4
Capacitance (Input to Output) CI-O 2.2 pF f = 1 MHz 11
Input Capacitance CI 4 pF 11
IC Junction to Ambient Thermal Resistance θJA 50.5 °C/W Thermocouple at center of package underside; 4-layer board with thin traces 11
Thermal Shutdown Threshold TSSD 150 °C TJ rising 11
Thermal Shutdown Hysteresis TSSD-HYS 20 °C 11
Operating Temperature TA -40 105 °C 13
Supply Voltage VDD1 at VISO = 5.0 V VDD1 4.5 5.5 V VDD1 at VISO = 5.0 V 13
Supply Voltage VDD1 at VISO = 3.3 V VDD1 3 3.6 V VDD1 at VISO = 3.3 V 13
Minimum Load IISO (MIN) 10 mA 13
Storage Temperature Range TST -55 150 °C 14
Ambient Operating Temperature Range TA -40 105 °C 14
Supply Voltage VDD1, VDDA, VDD2 VDD1, VDDA, VDD2 -0.5 7 V 14
Supply Voltage VREG, X1, X2 VREG, X1, X2 -0.5 20 V 14
Average Output Current per Pin -10 10 mA 14
Common-Mode Transients -100 100 kV/µs Across the insulation barrier 14
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration 12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474 is proof tested by applying an insulation test voltage of ≥1050 V peak for 1 sec (partial discha 11

CAD (KiCad official)

  • Symbol: ADUM3470ARSZ
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: adum3470arsz-etched.step / adum3470arsz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum3470arsz.step / adum3470arsz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (34 pp, sha256 f9c7011f1ea8066b, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF