ADUM342E0BRWZ from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Supply voltage for isolator side 1; this pin requires a 0.1 µF bypass capacitor.
2	GND1	power_in	Ground reference for isolator side 1.
3	VIA	input	Logic input A; per the truth table notes, input pins on a side with an unpowered supply must be held low to avoid powering the device through its ESD protection circuitry.
4	VIB	input	Logic input B; per the truth table notes, input pins on a side with an unpowered supply must be held low to avoid powering the device through its ESD protection circuitry.
5	VOC	output	Logic output C; it is enabled when VE2 is high or disconnected and is disabled to high-Z when VE2 is low.
6	VOD	output	Logic output D; it is enabled when VE2 is high or disconnected and is disabled to high-Z when VE2 is low.
7	VE1	input	Output enable 1, active high logic input; when VE1 is high or disconnected the VOA and VOB outputs are enabled, and when low they are disabled to high-Z.
8	GND1	power_in	Ground reference for isolator side 1.
9	GND2	power_in	Ground reference for isolator side 2.
10	VE2	input	Output enable 2, active high logic input; when VE2 is high or disconnected the VOC and VOD outputs are enabled, and when low they are disabled to high-Z.
11	VID	input	Logic input D; per the truth table notes, input pins on a side with an unpowered supply must be held low to avoid powering the device through its ESD protection circuitry.
12	VIC	input	Logic input C; per the truth table notes, input pins on a side with an unpowered supply must be held low to avoid powering the device through its ESD protection circuitry.
13	VOB	output	Logic output B; it is enabled when VE1 is high or disconnected and is disabled to high-Z when VE1 is low.
14	VOA	output	Logic output A; it is enabled when VE1 is high or disconnected and is disabled to high-Z when VE1 is low.
15	GND2	power_in	Ground reference for isolator side 2.
16	VDD2	power_in	Supply voltage for isolator side 2; this pin requires a 0.1 µF bypass capacitor.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-16
Category	Interface
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating Temperature (TA)	TA	-40		125	°C		17
Supply Voltage VDD1	VDD1	2.25		5.5	V		17
Supply Voltage VDD2	VDD2	2.25		5.5	V		17
Input Signal Rise and Fall Times				1	ms		17
Supply Voltage VDD1 to GND1 (absolute maximum)	VDD1 to GND1	-0.5		7	V		18
Supply Voltage VDD2 to GND2 (absolute maximum)	VDD2 to GND2	-0.5		7	V		18
Input Voltages (absolute maximum)	VIA, VIB, VIC, VID, VE1, VE2	-0.5			V		18
Output Voltages (absolute maximum)	VOA, VOB, VOC, VOD	-0.5			V		18
Side 1 Output Current (average per pin)	IO1	-10		10	mA	Average output current per pin	18
Side 2 Output Current (average per pin)	IO2	-10		10	mA	Average output current per pin	18
Common-Mode Transients		-300		300	kV/μs	Common-mode transients across the insulation barrier	18
Storage Temperature Range (TST)	TST	-65		150	°C		18
Ambient Operating Temperature Range (TA)	TA	-40		125	°C		18
Maximum Total Power Dissipation (safety limiting, RW-16)	PTOT			1.92	W	TA ≤ 25°C, PTOT = PSI = PSO	13
Propagation Delay [5 V operation]	tPHL, tPLH	3.5	6.2	10	ns	50% input to 50% output	5
Pulse Width Distortion [5 V operation]	PWD	0.3		3	ns	/tPLH − tPHL/	5
Channel Matching Codirectional [5 V operation]	tPSKCD	0.3		3	ns		5
Channel Matching Opposing Direction [5 V operation]	tPSKOD	0.3		3	ns		5
Output Enabled to High-Z [5 V operation]	tPHZ, tPLZ	3	5.5	12	ns	Output high/low to high impedance	5
Output High-Z to Enabled [5 V operation]	tPZH, tPZL	3	5.5	12	ns	Output high impedance to high/low	5
Output Logic Low VOL [5 V operation]	VOL	0		0.1	V	IOx = 20 µA, VIx = VIxL	5
Output Logic Low VOL [5 V operation]	VOL	0.2		0.4	V	IOx = 4 mA, VIx = VIxL	5
Input Current per Channel [5 V operation]	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx, 0 V ≤ VEx ≤ VDDx	5
Enable Input Pull-Up Current VE1, VE2 [5 V operation]	IPU	-10		-6	µA	VEx = 0 V	5
Tristate Output Current per Channel [5 V operation]	IOZ	-10	0.01	10	µA	0 V ≤ VOx ≤ VDDx, VEx ≤ VIL	5
Positive VDDx UVLO Threshold [5 V operation]	VUVLO+	2		2.2	V	Rising supply voltage enable threshold	6
Negative VDDx UVLO Threshold [5 V operation]	VUVLO−	1.7		1.8	V	Falling supply voltage lockout threshold	6
Common-Mode Transient Immunity CMH [5 V operation]	/CMH/	100		180	kV/µs	VIx = VDDx, VCM = 1000 V	6
Common-Mode Transient Immunity CML [5 V operation]	/CML/	100		180	kV/µs	VIx = 0 V, VCM = 1000 V	6
Quiescent Supply Current IDD1 (ADuM340E) [5 V]	IDD1 (Q)	0.61		0.85	mA	VI = 0 (E0), 1 (E1)	5
Quiescent Supply Current IDD2 (ADuM340E) [5 V]	IDD2 (Q)	1.5		2.3	mA	VI = 0 (E0), 1 (E1)	5
Quiescent Supply Current IDD1 (ADuM340E) [5 V]	IDD1 (Q)	7.6		11.2	mA	VI = 1 (E0), 0 (E1)	5
Quiescent Supply Current IDD2 (ADuM340E) [5 V]	IDD2 (Q)	3.3		5.1	mA	VI = 1 (E0), 0 (E1)	5
Quiescent Supply Current IDD1 (ADuM341E) [5 V]	IDD1 (Q)	0.8		1.3	mA	VI = 0 (E0), 1 (E1)	5
Quiescent Supply Current IDD2 (ADuM341E) [5 V]	IDD2 (Q)	1.3		1.9	mA	VI = 0 (E0), 1 (E1)	6
Quiescent Supply Current IDD1 (ADuM341E) [5 V]	IDD1 (Q)	6.3		9.2	mA	VI = 1 (E0), 0 (E1)	6
Quiescent Supply Current IDD2 (ADuM341E) [5 V]	IDD2 (Q)	4.2		6	mA	VI = 1 (E0), 0 (E1)	6
Quiescent Supply Current IDD1 (ADuM342E) [5 V]	IDD1 (Q)	1		1.7	mA	VI = 0 (E0), 1 (E1)	6
Quiescent Supply Current IDD2 (ADuM342E) [5 V]	IDD2 (Q)	1		1.7	mA	VI = 0 (E0), 1 (E1)	6
Quiescent Supply Current IDD1 (ADuM342E) [5 V]	IDD1 (Q)	5.2		8	mA	VI = 1 (E0), 0 (E1)	6
Quiescent Supply Current IDD2 (ADuM342E) [5 V]	IDD2 (Q)	5.3		7.8	mA	VI = 1 (E0), 0 (E1)	6
Junction-to-Air Thermal Impedance θJA (SOIC_W RW-16)	θJA		64.89		°C/W	JEDEC 2S2P board, no vias, still air	18
Junction-to-Board Thermal Impedance θJB (SOIC_W RW-16)	θJB		43.86		°C/W	JEDEC 2S2P board, no vias, still air	18
Board Characterization Parameter ΨJB (SOIC_W RW-16)	ΨJB		42.61		°C/W	JEDEC 2S2P board, no vias, still air	18
Package Top Characterization Parameter ΨJT (SOIC_W RW-16)	ΨJT		5.72		°C/W	JEDEC 2S2P board, no vias, still air	18
Propagation Delay Skew [5 V operation]	tPSK		6.1		ns	Between any two units at the same temperature, voltage, and load	5
Propagation Delay Change vs. Temperature [5 V operation]			1.5		ps/°C		5
Random Jitter RMS (1σ) [5 V operation]	tJIT(RJ)		7.19		ps	1 MHz clock input, all channels switching	5
Deterministic Jitter Peak-to-Peak [5 V operation]	tJIT(DJ)		223		ps	100 Mbps, 215 − 1 PRBS input	5
Total Jitter Peak-to-Peak without crosstalk [5 V operation]	tJIT(TJ)		292		ps	Single channel switching	5
Total Jitter Peak-to-Peak with crosstalk [5 V operation]	tJIT(TJ)		559		ps	All channels switching	5
Input Hysteresis VHYS [5 V operation]	VHYS		0.85		V	VIH − VIL	5
VDDx Hysteresis UVLO [5 V operation]	VUVLO_HYS		0.2		V	UVLO hysteresis	6
UVLO Release Time [5 V operation]	tUVLO		60		μs	UVLO release delay after VUVLO+ threshold	6
Output Rise/Fall Time [5 V operation]	tR/tF		2.5		ns	10% to 90%	6
Input Capacitance [5 V operation]	CI		4		pF		6
Dynamic Input Supply Current [5 V operation]	IDDI (D)		0.005		mA/Mbps	Inputs switching, 50% duty cycle	6
Dynamic Output Supply Current [5 V operation]	IDDO (D)		0.015		mA/Mbps	Inputs switching, 50% duty cycle, CL = 0 nF	6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pet		IEC 60747-17 (REINFORCED INSULATION) Maximum Repetitive Peak Isolation Voltage VIORM 1173 V peak	13

CAD (KiCad official)

Symbol: ADUM342E0BRWZ
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: adum342e0brwz-etched.step / adum342e0brwz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum342e0brwz.step / adum342e0brwz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 22b604b7fffd5710, retrieved 2026-11-04, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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ADUM342E0BRWZ

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