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ADUM342E0BRQZ

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Analog Devices , SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenticadum342e0brqzfactory-2.0.0extractor-text

Verified ADUM342E0BRQZ

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADUM342E0BRQZ · SOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 28-page datasheet
  • ✓distributor: lcsc C23159283, digikey 505-ADUM342E0BRQZ-ND, mouser 584-ADUM342E0BRQZ
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-o_gbc5qm/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ adum342e0brqz.kicad_sym✓ adum342e0brqz.kicad_mod✓ adum342e0brqz.step
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ADUM342E0BRQZ

Analog Devices · IC · SOP-16

ADUM342E0BRQZ from Analog Devices, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, requiring a 0.1 µF bypass capacitor (supply range 2.25 V to 5.5 V, absolute maximum 7.0 V to GND1).
2 GND1 power_in Ground reference for isolator side 1, connected internally in the package to pin 8.
3 VIA input Logic input A on side 1.
4 VIB input Logic input B on side 1.
5 VOC output Logic output C on side 1, disabled to high-Z when VE1 is low.
6 VOD output Logic output D on side 1, disabled to high-Z when VE1 is low.
7 VE1 input Output enable 1, active high; the VOA and VOB outputs are enabled when VE1 is high or disconnected and disabled to high-Z when VE1 is low.
8 GND1 power_in Ground reference for isolator side 1, connected internally in the package to pin 2.
9 GND2 power_in Ground reference for isolator side 2, connected internally in the package to pin 15.
10 VE2 input Output enable 2, active high; the VOC and VOD outputs are enabled when VE2 is high or disconnected and disabled to high-Z when VE2 is low.
11 VID input Logic input D on side 2.
12 VIC input Logic input C on side 2.
13 VOB output Logic output B on side 2, disabled to high-Z when VE2 is low.
14 VOA output Logic output A on side 2, disabled to high-Z when VE2 is low.
15 GND2 power_in Ground reference for isolator side 2, connected internally in the package to pin 9.
16 VDD2 power_in Supply voltage for isolator side 2, requiring a 0.1 µF bypass capacitor (supply range 2.25 V to 5.5 V, absolute maximum 7.0 V to GND2).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOP-16
Category
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Propagation Delay (5 V) tPHL, tPLH 3.5 6.2 10 ns 50% input to 50% output 5
Pulse Width Distortion (5 V) PWD 0.3 3 ns /tPLH − tPHL/ 5
Propagation Delay Skew (5 V) tPSK 6.1 ns Between any two units at the same temperature, voltage, and load 5
Channel Matching Codirectional (5 V) tPSKCD 0.3 3 ns 5
Channel Matching Opposing Direction (5 V) tPSKOD 0.3 3 ns 5
Output Enabled to High-Z (5 V) tPHZ, tPLZ 3 5.5 12 ns Output high/low to high impedance 5
Output High-Z to Enabled (5 V) tPZH, tPZL 3 5.5 12 ns Output high impedance to high/low 5
Output Voltage Logic Low (5 V, 20 µA) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 5
Output Voltage Logic Low (5 V, 4 mA) VOL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 5
Input Current per Channel (5 V) II -10 0.01 10 µA 0 V ≤ VIx ≤ VDDx, 0 V ≤ VEx ≤ VDDx 5
VE1, VE2 Enable Input Pull-Up Current (5 V) IPU -10 -6 µA VEx = 0 V 5
Tristate Output Current per Channel (5 V) IOZ -10 0.01 10 µA 0 V ≤ VOx ≤ VDDx, VEx ≤ VIL 5
Quiescent Supply Current Side 1, VI = 0 (E0) (5 V) IDD1 (Q) 1 1.7 mA VI = 0 (E0), 1 (E1) 6
Quiescent Supply Current Side 2, VI = 0 (E0) (5 V) IDD2 (Q) 1 1.7 mA VI = 0 (E0), 1 (E1) 6
Quiescent Supply Current Side 1, VI = 1 (E0) (5 V) IDD1 (Q) 5.2 8 mA VI = 1 (E0), 0 (E1) 6
Quiescent Supply Current Side 2, VI = 1 (E0) (5 V) IDD2 (Q) 5.3 7.8 mA VI = 1 (E0), 0 (E1) 6
Positive VDDx UVLO Threshold VUVLO+ 2 2.2 V Rising supply voltage enable threshold 6
Negative VDDx UVLO Threshold VUVLO− 1.7 1.8 V Falling supply voltage lockout threshold 6
Common-Mode Transient Immunity, High (5 V) /CMH/ 100 180 kV/µs VIx = VDDx, VCM = 1000 V 6
Common-Mode Transient Immunity, Low (5 V) /CML/ 100 180 kV/µs VIx = 0 V, VCM = 1000 V 6
Supply Current Side 1, 1 Mbps (5 V) IDD1 3.1 4.9 mA CL = 0 nF 7
Supply Current Side 2, 1 Mbps (5 V) IDD2 3.2 4.8 mA CL = 0 nF 7
Supply Current Side 1, 25 Mbps (5 V) IDD1 4.1 6.1 mA CL = 0 nF 7
Supply Current Side 2, 25 Mbps (5 V) IDD2 4.2 5.9 mA CL = 0 nF 7
Supply Current Side 1, 100 Mbps (5 V) IDD1 7.3 10 mA CL = 0 nF 7
Supply Current Side 2, 100 Mbps (5 V) IDD2 7.3 10 mA CL = 0 nF 7
Propagation Delay (3.3 V) tPHL, tPLH 3.6 6.6 10 ns 50% input to 50% output 8
Pulse Width Distortion (3.3 V) PWD 0.5 3 ns /tPLH − tPHL/ 8
Propagation Delay (2.5 V) tPHL, tPLH 4.1 7.2 14 ns 50% input to 50% output 11
Pulse Width Distortion (2.5 V) PWD 0.3 4.5 ns /tPLH − tPHL/ 11
Pulse Width (5 V) PW 6.6 ns Within pulse width distortion (PWD) limit 5
Data Rate (5 V) 150 Mbps Within PWD limit 5
Operating Temperature TA -40 125 °C 17
Supply Voltage VDD1 VDD1 2.25 5.5 V 17
Supply Voltage VDD2 VDD2 2.25 5.5 V 17
Input Signal Rise and Fall Times 1 ms 17
Supply Voltage VDD1 to GND1 VDD1 -0.5 7 V TA = 25°C 18
Supply Voltage VDD2 to GND2 VDD2 -0.5 7 V TA = 25°C 18
Input Voltages (VIA, VIB, VIC, VID, VE1, VE2) -0.5 V Upper limit VDDI + 0.5 V; TA = 25°C 18
Output Voltages (VOA, VOB, VOC, VOD) -0.5 V Upper limit VDDO + 0.5 V; TA = 25°C 18
Average Output Current per Pin, Side 1 IO1 -10 10 mA TA = 25°C 18
Average Output Current per Pin, Side 2 IO2 -10 10 mA TA = 25°C 18
Common-Mode Transients -300 300 kV/µs Across the insulation barrier 18
Storage Temperature Range TST -65 150 °C 18
Ambient Operating Temperature Range TA -40 125 °C 18
Junction-to-Ambient Thermal Resistance, QSOP (RQ-16) θJA 77.69 °C/W JEDEC 2S2P board, no vias, still air 18
Junction-to-Board Thermal Resistance, QSOP (RQ-16) θJB 43.19 °C/W JEDEC 2S2P board, no vias, still air 18
Junction-to-Board Characterization Parameter, QSOP (RQ-16) ΨJB 43.58 °C/W JEDEC 2S2P board, no vias, still air 18
Junction-to-Top Characterization Parameter, QSOP (RQ-16) ΨJT 0.92 °C/W JEDEC 2S2P board, no vias, still air 18
Maximum Withstanding Isolation Voltage, QSOP (RQ-16) VISO 3000 V rms VTEST = 1.2 × VISO, t = 1 s (100% production) 15
Maximum Repetitive Peak Isolation Voltage, QSOP (RQ-16) VIORM 566 V peak 15
Input Hysteresis (5 V) VHYS 0.85 V VIH − VIL 5
Input Capacitance (5 V) CI 4 pF 6
Dynamic Input Supply Current (5 V) IDDI (D) 0.005 mA/Mbps Inputs switching, 50% duty cycle 6
Dynamic Output Supply Current (5 V) IDDO (D) 0.015 mA/Mbps Inputs switching, 50% duty cycle, CL = 0 nF 6
Output Rise/Fall Time (5 V) tR/tF 2.5 ns 10% to 90% 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pet IEC 60747-17 (REINFORCED INSULATION) Maximum Repetitive Peak Isolation Voltage VIORM 1173 V peak 13

CAD (KiCad official)

  • Symbol: ADUM342E0BRQZ
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: adum342e0brqz-etched.step / adum342e0brqz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum342e0brqz.step / adum342e0brqz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 22b604b7fffd5710, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF