ADUM340E0BRQZ from Analog Devices, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Supply voltage for isolator side 1, which requires a 0.1 µF bypass capacitor.
2	GND1	power_in	Ground reference for isolator side 1.
3	VIA	input	Logic input A.
4	VIB	input	Logic input B.
5	VIC	input	Logic input C.
6	VID	input	Logic input D.
7	NIC	unconnected	No internal connection; leave this pin floating.
8	GND1	power_in	Ground reference for isolator side 1.
9	GND2	power_in	Ground reference for isolator side 2.
10	VE2	input	Output enable 2, active-high logic input; when low, VOA, VOB, VOC and VOD are disabled to the high-Z state, and when high or disconnected they are enabled.
11	VOD	output	Logic output D.
12	VOC	output	Logic output C.
13	VOB	output	Logic output B.
14	VOA	output	Logic output A.
15	GND2	power_in	Ground reference for isolator side 2.
16	VDD2	power_in	Supply voltage for isolator side 2, which requires a 0.1 µF bypass capacitor.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOP-16
Category
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage VDD1 (recommended operating)	VDD1	2.25		5.5	V		17
Supply Voltage VDD2 (recommended operating)	VDD2	2.25		5.5	V		17
Operating Temperature (recommended operating)	TA	-40		125	°C		17
Supply Voltage VDD1 to GND1 (absolute maximum)	VDD1	-0.5		7	V		18
Supply Voltage VDD2 to GND2 (absolute maximum)	VDD2	-0.5		7	V		18
Input Voltages (absolute maximum), max printed as VDDI + 0.5 V	VIA, VIB, VIC, VID, VE1, VE2	-0.5			V	Maximum printed as VDDI + 0.5 V (VDDI = input side supply)	18
Output Voltages (absolute maximum), max printed as VDDO + 0.5 V	VOA, VOB, VOC, VOD	-0.5			V	Maximum printed as VDDO + 0.5 V (VDDO = output side supply)	18
Side 1 Average Output Current per Pin (absolute maximum)	IO1	-10		10	mA	Average per pin; see Figure 4 for temperature-dependent maximum	18
Side 2 Average Output Current per Pin (absolute maximum)	IO2	-10		10	mA	Average per pin; see Figure 4 for temperature-dependent maximum	18
Common-Mode Transients (absolute maximum)		-300		300	kV/μs	Across the isolation barrier	18
Storage Temperature Range (absolute maximum)	TST	-65		150	°C		18
Ambient Operating Temperature Range (absolute maximum)	TA	-40		125	°C		18
Junction-to-Air Thermal Resistance (RQ-16 QSOP)	θJA		77.69		°C/W	Simulated, JEDEC 2S2P board, no vias, still air	18
Junction-to-Board Thermal Resistance (RQ-16 QSOP)	θJB		43.19		°C/W	Simulated, JEDEC 2S2P board, no vias, still air	18
Junction-to-Board Characterization Parameter (RQ-16 QSOP)	ΨJB		43.58		°C/W	Simulated, JEDEC 2S2P board, no vias, still air	18
Junction-to-Top Characterization Parameter (RQ-16 QSOP)	ΨJT		0.92		°C/W	Simulated, JEDEC 2S2P board, no vias, still air	18
Propagation Delay (5 V operation)	tPHL, tPLH	3.5	6.2	10	ns	50% input to 50% output	5
Output Enabled to High-Z (5 V operation)	tPHZ, tPLZ	3	5.5	12	ns	Output high/low to high impedance	5
Output High-Z to Enabled (5 V operation)	tPZH, tPZL	3	5.5	12	ns	Output high impedance to high/low	5
Input Current per Channel (5 V operation)	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx, 0 V ≤ VEx ≤ VDDx	5
Tristate Output Current per Channel (5 V operation)	IOZ	-10	0.01	10	µA	0 V ≤ VOx ≤ VDDx, VEx ≤ VIL	5
Propagation Delay (3.3 V operation)	tPHL, tPLH	3.6	6.6	10	ns	50% input to 50% output	8
Output Enabled to High-Z (3.3 V operation)	tPHZ, tPLZ	3	5	12	ns	Output high/low to high Impedance	8
Output High-Z to Enabled (3.3 V operation)	tPZH, tPZL	3	5	12	ns	Output high impedance to high/low	8
Input Current per Channel (3.3 V operation)	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx, 0 V ≤ VEx ≤ VDDx	8
Tristate Output Current per Channel (3.3 V operation)	IOZ	-10	0.01	10	µA	0 V ≤ VOx ≤ VDDx, VEx ≤ VIL	8
Propagation Delay (2.5 V operation)	tPHL, tPLH	4.1	7.2	14	ns	50% input to 50% output	11
Input Current per Channel (2.5 V operation)	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx	11
Tristate Output Current per Channel (2.5 V operation)	IOZ	-10	0.01	10	µA	0 V ≤ VOx ≤ VDDx, VEx ≤ VIL	11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pet		IEC 60747-17 (REINFORCED INSULATION) Maximum Repetitive Peak Isolation Voltage VIORM 1173 V peak	13

CAD (KiCad official)

Symbol: ADUM340E0BRQZ
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)
3D model files: adum340e0brqz-etched.step / adum340e0brqz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum340e0brqz.step / adum340e0brqz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 22b604b7fffd5710, retrieved 2026-11-04, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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ADUM340E0BRQZ

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