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ADUM3223BRZ-RL7
Public Made by Adomby adom
Analog Devices Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADUM3223BRZ-RL7
Analog Devices · Digital Isolators · SOIC-16
ADUM3223BRZ-RL7 from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIA | input | Logic input A, a CMOS input referenced to GND1 with absolute maximum range of −0.5 V to VDD1 + 0.5 V. |
| 2 | VIB | input | Logic input B, a CMOS input referenced to GND1 with absolute maximum range of −0.5 V to VDD1 + 0.5 V. |
| 3 | VDD1 | power_in | Input supply voltage, recommended 3.0 V to 5.5 V; internally connected to pin 8, and both pins should be connected to VDD1. |
| 4 | GND1 | power_in | Ground reference for the input logic signals. |
| 5 | DISABLE | input | Input disable: when driven high the input isolator is disabled and the outputs go to the default low state within 3 µs, and they return to the input state within 1 µs after DISABLE is set low. |
| 6 | NC | unconnected | No connect; do not connect to this pin. |
| 7 | NC | unconnected | No connect; do not connect to this pin. |
| 8 | VDD1 | power_in | Input supply voltage, recommended 3.0 V to 5.5 V; internally connected to pin 3, and both pins should be connected to VDD1. |
| 9 | GNDB | power_in | Ground reference for output B. |
| 10 | VOB | output | Output B driver, rated for 4 A peak output current with a gate driver supply of 4.5 V to 18 V (VDDB). |
| 11 | VDDB | power_in | Output B supply voltage, recommended 4.5 V to 18 V, with absolute maximum of −0.5 V to +20 V. |
| 12 | NC | unconnected | No connect; do not connect to this pin. |
| 13 | NC | unconnected | No connect; do not connect to this pin. |
| 14 | GNDA | power_in | Ground reference for output A. |
| 15 | VOA | output | Output A driver, rated for 4 A peak output current with a gate driver supply of 4.5 V to 18 V (VDDA). |
| 16 | VDDA | power_in | Output A supply voltage, recommended 4.5 V to 18 V, with absolute maximum of −0.5 V to +20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply current, quiescent (VDD1, 5 V table) | IDDI(Q) | 1.4 | 2.4 | mA | 3 | ||
| Output supply current, quiescent per channel (5 V table) | IDDO(Q) | 2.3 | 3.2 | mA | 3 | ||
| VDD1 supply current (5 V table) | IDD1(Q) | 1.6 | 2.5 | mA | Up to 1 MHz, unloaded | 3 | |
| VDDA/VDDB supply current (5 V table) | IDDA/IDDB(Q) | 5.6 | 8 | mA | Up to 1 MHz, unloaded | 3 | |
| Input current | IIA, IIB | -1 | 0.01 | 1 | µA | 0 ≤ VIA, VIB ≤ VDD1 | 3 |
| Logic low output voltage (5 V table) | VOAL, VOBL | 0 | 0.15 | V | IOx = +20 mA, VIx = VIxL | 3 | |
| VDD2 undervoltage lockout positive threshold, B grade | VDD2UV+ | 6.9 | 7.4 | V | B级 | 3 | |
| VDD2 undervoltage lockout negative threshold, B grade | VDD2UV− | 5.7 | 6.2 | V | B级 | 3 | |
| VDD2 undervoltage lockout hysteresis, B grade | VDD2UVH | 0.7 | V | B级 | 3 | ||
| Output short-circuit pulse current | IOA(SC), IOB(SC) | 2 | 4 | A | VDD2 = 12 V | 3 | |
| Output pulse source resistance | ROA, ROB | 0.3 | 1.1 | 3 | Ω | VDD2 = 12 V | 3 |
| Output pulse sink resistance | ROA, ROB | 0.3 | 0.6 | 3 | Ω | VDD2 = 12 V | 3 |
| Thermal shutdown junction temperature, rising edge | TJR | 150 | °C | 3 | |||
| Thermal shutdown junction temperature, falling edge | TJF | 140 | °C | 3 | |||
| Pulse width | PW | 50 | ns | CL = 2 nF, VDD2 = 12 V | 3 | ||
| Maximum data rate | 1 | MHz | CL = 2 nF, VDD2 = 12 V | 3 | |||
| Propagation delay (B/C variants, 5 V table) | tDHL, tDLH | 31 | 43 | 54 | ns | CL = 2 nF, VDD2 = 12 V | 3 |
| Propagation delay skew | tPSK | 12 | ns | CL = 2 nF, VDD2 = 12 V; see Figure 20 | 3 | ||
| Channel-to-channel matching (5 V table) | tPSKCD | 5 | ns | CL = 2 nF, VDD2 = 12 V; see Figure 20 | 3 | ||
| Channel-to-channel matching (5 V table) | tPSKCD | 7 | ns | CL = 2 nF, VDD2 = 4.5 V; see Figure 20 | 3 | ||
| Output rise/fall time 10% to 90% (5 V table) | tR/tF | 6 | 12 | 18 | ns | CL = 2 nF, VDD2 = 12 V; see Figure 20 | 3 |
| Dynamic input supply current per channel | IDDI(D) | 0.05 | mA/Mbps | VDD2 = 12 V | 3 | ||
| Dynamic output supply current per channel | IDDO(D) | 1.65 | mA/Mbps | VDD2 = 12 V | 3 | ||
| Refresh rate | fr | 1.2 | Mbps | 3 | |||
| Input supply current, quiescent (VDD1 3.3 V table) | IDDI(Q) | 0.87 | 1.4 | mA | 4 | ||
| Output supply current, quiescent per channel (3.3 V table) | IDDO(Q) | 2.3 | 3.2 | mA | 4 | ||
| VDD1 supply current (3.3 V table) | IDD1(Q) | 1.1 | 1.5 | mA | Up to 1 MHz, unloaded | 4 | |
| VDDA/VDDB supply current (3.3 V table) | IDDA/IDDB(Q) | 5.6 | 8 | mA | Up to 1 MHz, unloaded | 4 | |
| Input current (3.3 V table) | IIA, IIB | -10 | 0.01 | 10 | µA | 0 ≤ VIA, VIB ≤ VDD1 | 4 |
| Logic low output voltage (3.3 V table) | VOAL, VOBL | 0 | 0.15 | V | IOx = +20 mA, VIx = VIxL | 4 | |
| Propagation delay (B/C variants, 3.3 V table) | tDHL, tDLH | 35 | 47 | 59 | ns | CL = 2 nF, VDD2 = 12 V, see Figure 20 | 4 |
| Output rise/fall time 10% to 90% (3.3 V table) | tR/tF | 6 | 12 | 22 | ns | CL = 2 nF, VDD2 = 12 V; see Figure 20 | 4 |
| Absolute maximum storage temperature | TST | -55 | 150 | °C | Ambient = 25°C unless noted | 9 | |
| Absolute maximum operating junction temperature | TJ | -40 | 150 | °C | 9 | ||
| Absolute maximum VDD1 supply voltage | VDD1 | -0.5 | 7 | V | Referenced to GND1 | 9 | |
| Absolute maximum VDDA/VDDB supply voltage | VDDA, VDDB | -0.5 | 20 | V | Referenced to GNDA/GNDB | 9 | |
| Absolute maximum average output current per pin | IO | -35 | 35 | mA | 9 | ||
| Absolute maximum common-mode transient | CMH, CML | -100 | 100 | kV/µs | Across isolation barrier | 9 | |
| Recommended operating junction temperature | TJ | -40 | 125 | °C | 8 | ||
| Recommended VDD1 supply voltage | VDD1 | 3 | 5.5 | V | Referenced to GND1 | 8 | |
| Recommended VDDA, VDDB supply voltage | VDDA, VDDB | 4.5 | 18 | V | Referenced to GNDA/GNDB | 8 | |
| Recommended VDD1 supply rise time | TVDD1 | 1 | V/µs | 8 | |||
| Recommended VDDA, VDDB supply rise time | TVDDA, TVDDB | 10 | V/µs | 8 | |||
| Recommended maximum input signal rise and fall time | TVIA, TVIB | 1 | ms | 8 | |||
| Common-mode transient immunity, static | -50 | 50 | kV/µs | 8 | |||
| Common-mode transient immunity, dynamic | -25 | 25 | kV/µs | 8 | |||
| Junction-to-ambient thermal resistance (ADuM3223, narrow body) | θJA | 76 | °C/W | 5 | |||
| Junction-to-case thermal resistance (ADuM3223, narrow body) | θJC | 42 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
ADUM3223BRZ-RL7 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
adum3223brz-rl7-etched.step/adum3223brz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum3223brz-rl7.step/adum3223brz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
c76e8bfb8d7a103c, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADUM3223BRZ-RL7
**Analog Devices** · Digital Isolators · SOIC-16
ADUM3223BRZ-RL7 from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIA | input | Logic input A, a CMOS input referenced to GND1 with absolute maximum range of −0.5 V to VDD1 + 0.5 V. |
| 2 | VIB | input | Logic input B, a CMOS input referenced to GND1 with absolute maximum range of −0.5 V to VDD1 + 0.5 V. |
| 3 | VDD1 | power_in | Input supply voltage, recommended 3.0 V to 5.5 V; internally connected to pin 8, and both pins should be connected to VDD1. |
| 4 | GND1 | power_in | Ground reference for the input logic signals. |
| 5 | DISABLE | input | Input disable: when driven high the input isolator is disabled and the outputs go to the default low state within 3 µs, and they return to the input state within 1 µs after DISABLE is set low. |
| 6 | NC | unconnected | No connect; do not connect to this pin. |
| 7 | NC | unconnected | No connect; do not connect to this pin. |
| 8 | VDD1 | power_in | Input supply voltage, recommended 3.0 V to 5.5 V; internally connected to pin 3, and both pins should be connected to VDD1. |
| 9 | GNDB | power_in | Ground reference for output B. |
| 10 | VOB | output | Output B driver, rated for 4 A peak output current with a gate driver supply of 4.5 V to 18 V (VDDB). |
| 11 | VDDB | power_in | Output B supply voltage, recommended 4.5 V to 18 V, with absolute maximum of −0.5 V to +20 V. |
| 12 | NC | unconnected | No connect; do not connect to this pin. |
| 13 | NC | unconnected | No connect; do not connect to this pin. |
| 14 | GNDA | power_in | Ground reference for output A. |
| 15 | VOA | output | Output A driver, rated for 4 A peak output current with a gate driver supply of 4.5 V to 18 V (VDDA). |
| 16 | VDDA | power_in | Output A supply voltage, recommended 4.5 V to 18 V, with absolute maximum of −0.5 V to +20 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply current, quiescent (VDD1, 5 V table) | IDDI(Q) | | 1.4 | 2.4 | mA | | 3 |
| Output supply current, quiescent per channel (5 V table) | IDDO(Q) | | 2.3 | 3.2 | mA | | 3 |
| VDD1 supply current (5 V table) | IDD1(Q) | | 1.6 | 2.5 | mA | Up to 1 MHz, unloaded | 3 |
| VDDA/VDDB supply current (5 V table) | IDDA/IDDB(Q) | | 5.6 | 8 | mA | Up to 1 MHz, unloaded | 3 |
| Input current | IIA, IIB | -1 | 0.01 | 1 | µA | 0 ≤ VIA, VIB ≤ VDD1 | 3 |
| Logic low output voltage (5 V table) | VOAL, VOBL | | 0 | 0.15 | V | IOx = +20 mA, VIx = VIxL | 3 |
| VDD2 undervoltage lockout positive threshold, B grade | VDD2UV+ | 6.9 | | 7.4 | V | B级 | 3 |
| VDD2 undervoltage lockout negative threshold, B grade | VDD2UV− | 5.7 | | 6.2 | V | B级 | 3 |
| VDD2 undervoltage lockout hysteresis, B grade | VDD2UVH | | 0.7 | | V | B级 | 3 |
| Output short-circuit pulse current | IOA(SC), IOB(SC) | 2 | 4 | | A | VDD2 = 12 V | 3 |
| Output pulse source resistance | ROA, ROB | 0.3 | 1.1 | 3 | Ω | VDD2 = 12 V | 3 |
| Output pulse sink resistance | ROA, ROB | 0.3 | 0.6 | 3 | Ω | VDD2 = 12 V | 3 |
| Thermal shutdown junction temperature, rising edge | TJR | | 150 | | °C | | 3 |
| Thermal shutdown junction temperature, falling edge | TJF | | 140 | | °C | | 3 |
| Pulse width | PW | 50 | | | ns | CL = 2 nF, VDD2 = 12 V | 3 |
| Maximum data rate | | | | 1 | MHz | CL = 2 nF, VDD2 = 12 V | 3 |
| Propagation delay (B/C variants, 5 V table) | tDHL, tDLH | 31 | 43 | 54 | ns | CL = 2 nF, VDD2 = 12 V | 3 |
| Propagation delay skew | tPSK | | | 12 | ns | CL = 2 nF, VDD2 = 12 V; see Figure 20 | 3 |
| Channel-to-channel matching (5 V table) | tPSKCD | | | 5 | ns | CL = 2 nF, VDD2 = 12 V; see Figure 20 | 3 |
| Channel-to-channel matching (5 V table) | tPSKCD | | | 7 | ns | CL = 2 nF, VDD2 = 4.5 V; see Figure 20 | 3 |
| Output rise/fall time 10% to 90% (5 V table) | tR/tF | 6 | 12 | 18 | ns | CL = 2 nF, VDD2 = 12 V; see Figure 20 | 3 |
| Dynamic input supply current per channel | IDDI(D) | | 0.05 | | mA/Mbps | VDD2 = 12 V | 3 |
| Dynamic output supply current per channel | IDDO(D) | | 1.65 | | mA/Mbps | VDD2 = 12 V | 3 |
| Refresh rate | fr | | 1.2 | | Mbps | | 3 |
| Input supply current, quiescent (VDD1 3.3 V table) | IDDI(Q) | | 0.87 | 1.4 | mA | | 4 |
| Output supply current, quiescent per channel (3.3 V table) | IDDO(Q) | | 2.3 | 3.2 | mA | | 4 |
| VDD1 supply current (3.3 V table) | IDD1(Q) | | 1.1 | 1.5 | mA | Up to 1 MHz, unloaded | 4 |
| VDDA/VDDB supply current (3.3 V table) | IDDA/IDDB(Q) | | 5.6 | 8 | mA | Up to 1 MHz, unloaded | 4 |
| Input current (3.3 V table) | IIA, IIB | -10 | 0.01 | 10 | µA | 0 ≤ VIA, VIB ≤ VDD1 | 4 |
| Logic low output voltage (3.3 V table) | VOAL, VOBL | | 0 | 0.15 | V | IOx = +20 mA, VIx = VIxL | 4 |
| Propagation delay (B/C variants, 3.3 V table) | tDHL, tDLH | 35 | 47 | 59 | ns | CL = 2 nF, VDD2 = 12 V, see Figure 20 | 4 |
| Output rise/fall time 10% to 90% (3.3 V table) | tR/tF | 6 | 12 | 22 | ns | CL = 2 nF, VDD2 = 12 V; see Figure 20 | 4 |
| Absolute maximum storage temperature | TST | -55 | | 150 | °C | Ambient = 25°C unless noted | 9 |
| Absolute maximum operating junction temperature | TJ | -40 | | 150 | °C | | 9 |
| Absolute maximum VDD1 supply voltage | VDD1 | -0.5 | | 7 | V | Referenced to GND1 | 9 |
| Absolute maximum VDDA/VDDB supply voltage | VDDA, VDDB | -0.5 | | 20 | V | Referenced to GNDA/GNDB | 9 |
| Absolute maximum average output current per pin | IO | -35 | | 35 | mA | | 9 |
| Absolute maximum common-mode transient | CMH, CML | -100 | | 100 | kV/µs | Across isolation barrier | 9 |
| Recommended operating junction temperature | TJ | -40 | | 125 | °C | | 8 |
| Recommended VDD1 supply voltage | VDD1 | 3 | | 5.5 | V | Referenced to GND1 | 8 |
| Recommended VDDA, VDDB supply voltage | VDDA, VDDB | 4.5 | | 18 | V | Referenced to GNDA/GNDB | 8 |
| Recommended VDD1 supply rise time | TVDD1 | | | 1 | V/µs | | 8 |
| Recommended VDDA, VDDB supply rise time | TVDDA, TVDDB | | | 10 | V/µs | | 8 |
| Recommended maximum input signal rise and fall time | TVIA, TVIB | | | 1 | ms | | 8 |
| Common-mode transient immunity, static | | -50 | | 50 | kV/µs | | 8 |
| Common-mode transient immunity, dynamic | | -25 | | 25 | kV/µs | | 8 |
| Junction-to-ambient thermal resistance (ADuM3223, narrow body) | θJA | | 76 | | °C/W | | 5 |
| Junction-to-case thermal resistance (ADuM3223, narrow body) | θJC | | 42 | | °C/W | | 5 |
## CAD (KiCad official)
- Symbol: `ADUM3223BRZ-RL7`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `adum3223brz-rl7-etched.step` / `adum3223brz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adum3223brz-rl7.step` / `adum3223brz-rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907877213327360) (20 pp, sha256 `c76e8bfb8d7a103c`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adum3223brz-rl7-datasheet.pdf)