component
ADUM3221BRZ
Public Made by Adomby adom
Analog Devices Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
ADUM3221BRZ
Analog Devices · Gate Drive ICs · SOIC-8
ADUM3221BRZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified at 3.0 V to 5.5 V. |
| 2 | VIA | input | Logic Input A on the side 1 input; CMOS logic high threshold is 0.7 × VDD1 and low threshold is 0.3 × VDD1 per the electrical characteristics. |
| 3 | VIB | input | Logic Input B on the side 1 input; CMOS logic high threshold is 0.7 × VDD1 and low threshold is 0.3 × VDD1 per the electrical characteristics. |
| 4 | GND1 | power_in | Ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground reference for isolator side 2. |
| 6 | VOB | output | Logic Output B on the side 2 output; logic low output is specified at 0.15 V maximum at IOx = +20 mA and logic high is VDD2 − 0.1 V minimum at IOx = −20 mA. |
| 7 | VOA | output | Logic Output A on the side 2 output; logic low output is specified at 0.15 V maximum at IOx = +20 mA and logic high is VDD2 − 0.1 V minimum at IOx = −20 mA. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2, specified at 4.5 V to 18 V in the pin function table. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Power Supply Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Current, Two Channels, Quiescent (5 V operation table) | IDDI(Q) | 1.2 | 1.5 | mA | 3 | ||
| Output Supply Current, Two Channels, Quiescent | IDDO(Q) | 4.7 | 10 | mA | 3 | ||
| VDD1 Supply Current (5 V operation table) | IDD1(Q) | 1.4 | 1.7 | mA | DC to 1 MHz logic signal frequency | 3 | |
| VDD2 Supply Current | IDD2(Q) | 11 | 17 | mA | DC to 1 MHz logic signal frequency | 3 | |
| Input Currents | IIA, IIB | -10 | 0.01 | 10 | µA | 0 V ≤ VIA, VIB ≤ VDD1 | 3 |
| Logic Low Output Voltages | VOAL, VOBL | 0 | 0.15 | V | IOx = +20 mA, VIx = VIxL | 3 | |
| Undervoltage Lockout VDD2 Positive-Going Threshold (ADuM3221B) | VDD2UV+ | 7 | 7.5 | V | 3 | ||
| Undervoltage Lockout VDD2 Negative-Going Threshold (ADuM3221B) | VDD2UV− | 6 | 6.5 | V | 3 | ||
| Undervoltage Lockout VDD2 Hysteresis (ADuM3221B) | VDD2UVH | 0.5 | V | 3 | |||
| Output Short-Circuit Pulsed Current | IOA(SC), IOB(SC) | 2 | 4 | A | VDD2 = 10 V | 3 | |
| Output Pulsed Source Resistance | ROA, ROB | 0.3 | 1.3 | 3 | Ω | VDD2 = 10 V | 3 |
| Output Pulsed Sink Resistance | ROA, ROB | 0.3 | 0.9 | 3 | Ω | VDD2 = 10 V | 3 |
| Pulse Width | PW | 50 | ns | CL = 2 nF, VDD2 = 10 V | 3 | ||
| Data Rate | 1 | MHz | CL = 2 nF, VDD2 = 10 V | 3 | |||
| Propagation Delay (5 V operation table, VDD2 = 10 V) | tDLH, tDHL | 35 | 45 | 60 | ns | CL = 2 nF, VDD2 = 10 V; see Figure 20 | 3 |
| Propagation Delay (5 V operation table, VDD2 = 4.5 V) | tDLH, tDHL | 36 | 50 | 68 | ns | CL = 2 nF, VDD2 = 4.5 V; see Figure 20 | 3 |
| Propagation Delay Skew | tPSK | 12 | ns | CL = 2 nF, VDD2 = 10 V; see Figure 20 | 3 | ||
| Channel-to-Channel Matching (VDD2 = 10 V) | tPSKCD | 1 | 5 | ns | CL = 2 nF, VDD2 = 10 V; see Figure 20 | 3 | |
| Channel-to-Channel Matching (VDD2 = 4.5 V) | tPSKCD | 1 | 7 | ns | CL = 2 nF, VDD2 = 4.5 V; see Figure 20 | 3 | |
| Output Rise/Fall Time (10% to 90%), VDD2 = 10 V | tR/tF | 14 | 20 | 25 | ns | CL = 2 nF, VDD2 = 10 V; see Figure 20 | 3 |
| Output Rise/Fall Time (10% to 90%), VDD2 = 4.5 V | tR/tF | 14 | 22 | 28 | ns | CL = 2 nF, VDD2 = 4.5 V; see Figure 20 | 3 |
| Dynamic Input Supply Current per Channel (5 V operation table) | IDDI(D) | 0.05 | mA/Mbps | VDD2 = 10 V | 3 | ||
| Dynamic Output Supply Current per Channel | IDDO(D) | 1.5 | mA/Mbps | VDD2 = 10 V | 3 | ||
| Refresh Rate (5 V operation table) | fr | 1.2 | Mbps | 3 | |||
| Input Supply Current, Two Channels, Quiescent (3.3 V operation table) | IDDI(Q) | 0.7 | 1 | mA | 4 | ||
| VDD1 Supply Current (3.3 V operation table) | IDD1(Q) | 0.8 | 1 | mA | DC to 1 MHz logic signal frequency | 4 | |
| Propagation Delay (3.3 V operation table, VDD2 = 10 V) | tDLH, tDHL | 36 | 48 | 62 | ns | CL = 2 nF, VDD2 = 10 V; see Figure 20 | 4 |
| Propagation Delay (3.3 V operation table, VDD2 = 4.5 V) | tDLH, tDHL | 37 | 53 | 72 | ns | CL = 2 nF, VDD2 = 4.5 V; see Figure 20 | 4 |
| Dynamic Input Supply Current per Channel (3.3 V operation table) | IDDI(D) | 0.025 | mA/Mbps | VDD2 = 10 V | 4 | ||
| Refresh Rate (3.3 V operation table) | fr | 1.1 | Mbps | 4 | |||
| Operating Junction Temperature | TJ | -40 | 125 | °C | 6 | ||
| Supply Voltage VDD1 | VDD1 | 3 | 5.5 | V | All voltages relative to their respective ground | 6 | |
| Supply Voltage VDD2 | VDD2 | 4.5 | 18 | V | All voltages relative to their respective ground | 6 | |
| VDD1 Rise Time | tVDD1 | 1 | V/µs | 6 | |||
| Common-Mode Transient Immunity, Input to Output | -25 | 25 | kV/µs | 6 | |||
| Input Signal Rise and Fall Times | 1 | ms | 6 | ||||
| Minimum VDD2 Operating Voltage (ADuM3221BRZ, per ordering guide) | VDD2 | 7.6 | V | B grade variant | 15 | ||
| Storage Temperature | TST | -55 | 150 | °C | 7 | ||
| Operating Temperature | TJ | -40 | 150 | °C | 7 | ||
| Supply Voltage Range VDD1 | VDD1 | -0.5 | 7 | V | 7 | ||
| Supply Voltage Range VDD2 | VDD2 | -0.5 | 20 | V | 7 | ||
| Input Voltage Range (VIA, VIB) | VIA, VIB | -0.5 | V | Upper limit printed as VDDI + 0.5 V | 7 | ||
| Output Voltage Range (VOA, VOB) | VOA, VOB | -0.5 | V | Upper limit printed as VDDO + 0.5 V | 7 | ||
| Average Output Current per Pin | IO | -23 | 23 | mA | See Figure 3 for temperature derating | 7 | |
| VOA to GND2 Negative Transient | VOA | -2 | V | 200 ns; nonautomotive grade devices only | 7 | ||
| VOB to GND2 Negative Transient | VOB | -2 | V | 200 ns; nonautomotive grade devices only | 7 | ||
| Common-Mode Transients | CMH, CML | -100 | 100 | kV/µs | 7 | ||
| AC Bipolar Voltage (max continuous working voltage) | 565 | V peak | 50-year minimum lifetime | 7 | |||
| AC Unipolar Voltage (max continuous working voltage) | 1131 | V peak | 50-year minimum lifetime | 7 | |||
| DC Voltage (max continuous working voltage) | 1131 | V peak | 50-year minimum lifetime | 7 | |||
| IC Junction-to-Case Thermal Resistance, Side 1 | θJCI | 46 | °C/W | Thermocouple located at center of package underside | 5 | ||
| IC Junction-to-Case Thermal Resistance, Side 2 | θJCO | 41 | °C/W | Thermocouple located at center of package underside | 5 | ||
| IC Junction-to-Ambient Thermal Resistance | θJA | 85 | °C/W | Thermocouple located at center of package underside | 5 | ||
| Capacitance (Input-to-Output) | CI-O | 1 | pF | f = 1 MHz | 5 | ||
| Input Capacitance | CI | 4 | pF | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | limit = 5 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM3220/ADuM3221 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 | 5 |
CAD (KiCad official)
- Symbol:
ADUM3221BRZ - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
adum3221brz-etched.step/adum3221brz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum3221brz.step/adum3221brz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (16 pp, sha256
9d99041c90842985, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADUM3221BRZ
**Analog Devices** · Gate Drive ICs · SOIC-8
ADUM3221BRZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified at 3.0 V to 5.5 V. |
| 2 | VIA | input | Logic Input A on the side 1 input; CMOS logic high threshold is 0.7 × VDD1 and low threshold is 0.3 × VDD1 per the electrical characteristics. |
| 3 | VIB | input | Logic Input B on the side 1 input; CMOS logic high threshold is 0.7 × VDD1 and low threshold is 0.3 × VDD1 per the electrical characteristics. |
| 4 | GND1 | power_in | Ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground reference for isolator side 2. |
| 6 | VOB | output | Logic Output B on the side 2 output; logic low output is specified at 0.15 V maximum at IOx = +20 mA and logic high is VDD2 − 0.1 V minimum at IOx = −20 mA. |
| 7 | VOA | output | Logic Output A on the side 2 output; logic low output is specified at 0.15 V maximum at IOx = +20 mA and logic high is VDD2 − 0.1 V minimum at IOx = −20 mA. |
| 8 | VDD2 | power_in | Supply voltage for isolator side 2, specified at 4.5 V to 18 V in the pin function table. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Power Supply Chip |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Current, Two Channels, Quiescent (5 V operation table) | IDDI(Q) | | 1.2 | 1.5 | mA | | 3 |
| Output Supply Current, Two Channels, Quiescent | IDDO(Q) | | 4.7 | 10 | mA | | 3 |
| VDD1 Supply Current (5 V operation table) | IDD1(Q) | | 1.4 | 1.7 | mA | DC to 1 MHz logic signal frequency | 3 |
| VDD2 Supply Current | IDD2(Q) | | 11 | 17 | mA | DC to 1 MHz logic signal frequency | 3 |
| Input Currents | IIA, IIB | -10 | 0.01 | 10 | µA | 0 V ≤ VIA, VIB ≤ VDD1 | 3 |
| Logic Low Output Voltages | VOAL, VOBL | 0 | | 0.15 | V | IOx = +20 mA, VIx = VIxL | 3 |
| Undervoltage Lockout VDD2 Positive-Going Threshold (ADuM3221B) | VDD2UV+ | 7 | 7.5 | | V | | 3 |
| Undervoltage Lockout VDD2 Negative-Going Threshold (ADuM3221B) | VDD2UV− | 6 | 6.5 | | V | | 3 |
| Undervoltage Lockout VDD2 Hysteresis (ADuM3221B) | VDD2UVH | | 0.5 | | V | | 3 |
| Output Short-Circuit Pulsed Current | IOA(SC), IOB(SC) | 2 | 4 | | A | VDD2 = 10 V | 3 |
| Output Pulsed Source Resistance | ROA, ROB | 0.3 | 1.3 | 3 | Ω | VDD2 = 10 V | 3 |
| Output Pulsed Sink Resistance | ROA, ROB | 0.3 | 0.9 | 3 | Ω | VDD2 = 10 V | 3 |
| Pulse Width | PW | 50 | | | ns | CL = 2 nF, VDD2 = 10 V | 3 |
| Data Rate | | | | 1 | MHz | CL = 2 nF, VDD2 = 10 V | 3 |
| Propagation Delay (5 V operation table, VDD2 = 10 V) | tDLH, tDHL | 35 | 45 | 60 | ns | CL = 2 nF, VDD2 = 10 V; see Figure 20 | 3 |
| Propagation Delay (5 V operation table, VDD2 = 4.5 V) | tDLH, tDHL | 36 | 50 | 68 | ns | CL = 2 nF, VDD2 = 4.5 V; see Figure 20 | 3 |
| Propagation Delay Skew | tPSK | | | 12 | ns | CL = 2 nF, VDD2 = 10 V; see Figure 20 | 3 |
| Channel-to-Channel Matching (VDD2 = 10 V) | tPSKCD | | 1 | 5 | ns | CL = 2 nF, VDD2 = 10 V; see Figure 20 | 3 |
| Channel-to-Channel Matching (VDD2 = 4.5 V) | tPSKCD | | 1 | 7 | ns | CL = 2 nF, VDD2 = 4.5 V; see Figure 20 | 3 |
| Output Rise/Fall Time (10% to 90%), VDD2 = 10 V | tR/tF | 14 | 20 | 25 | ns | CL = 2 nF, VDD2 = 10 V; see Figure 20 | 3 |
| Output Rise/Fall Time (10% to 90%), VDD2 = 4.5 V | tR/tF | 14 | 22 | 28 | ns | CL = 2 nF, VDD2 = 4.5 V; see Figure 20 | 3 |
| Dynamic Input Supply Current per Channel (5 V operation table) | IDDI(D) | | 0.05 | | mA/Mbps | VDD2 = 10 V | 3 |
| Dynamic Output Supply Current per Channel | IDDO(D) | | 1.5 | | mA/Mbps | VDD2 = 10 V | 3 |
| Refresh Rate (5 V operation table) | fr | | 1.2 | | Mbps | | 3 |
| Input Supply Current, Two Channels, Quiescent (3.3 V operation table) | IDDI(Q) | | 0.7 | 1 | mA | | 4 |
| VDD1 Supply Current (3.3 V operation table) | IDD1(Q) | | 0.8 | 1 | mA | DC to 1 MHz logic signal frequency | 4 |
| Propagation Delay (3.3 V operation table, VDD2 = 10 V) | tDLH, tDHL | 36 | 48 | 62 | ns | CL = 2 nF, VDD2 = 10 V; see Figure 20 | 4 |
| Propagation Delay (3.3 V operation table, VDD2 = 4.5 V) | tDLH, tDHL | 37 | 53 | 72 | ns | CL = 2 nF, VDD2 = 4.5 V; see Figure 20 | 4 |
| Dynamic Input Supply Current per Channel (3.3 V operation table) | IDDI(D) | | 0.025 | | mA/Mbps | VDD2 = 10 V | 4 |
| Refresh Rate (3.3 V operation table) | fr | | 1.1 | | Mbps | | 4 |
| Operating Junction Temperature | TJ | -40 | | 125 | °C | | 6 |
| Supply Voltage VDD1 | VDD1 | 3 | | 5.5 | V | All voltages relative to their respective ground | 6 |
| Supply Voltage VDD2 | VDD2 | 4.5 | | 18 | V | All voltages relative to their respective ground | 6 |
| VDD1 Rise Time | tVDD1 | | | 1 | V/µs | | 6 |
| Common-Mode Transient Immunity, Input to Output | | -25 | | 25 | kV/µs | | 6 |
| Input Signal Rise and Fall Times | | | | 1 | ms | | 6 |
| Minimum VDD2 Operating Voltage (ADuM3221BRZ, per ordering guide) | VDD2 | 7.6 | | | V | B grade variant | 15 |
| Storage Temperature | TST | -55 | | 150 | °C | | 7 |
| Operating Temperature | TJ | -40 | | 150 | °C | | 7 |
| Supply Voltage Range VDD1 | VDD1 | -0.5 | | 7 | V | | 7 |
| Supply Voltage Range VDD2 | VDD2 | -0.5 | | 20 | V | | 7 |
| Input Voltage Range (VIA, VIB) | VIA, VIB | -0.5 | | | V | Upper limit printed as VDDI + 0.5 V | 7 |
| Output Voltage Range (VOA, VOB) | VOA, VOB | -0.5 | | | V | Upper limit printed as VDDO + 0.5 V | 7 |
| Average Output Current per Pin | IO | -23 | | 23 | mA | See Figure 3 for temperature derating | 7 |
| VOA to GND2 Negative Transient | VOA | -2 | | | V | 200 ns; nonautomotive grade devices only | 7 |
| VOB to GND2 Negative Transient | VOB | -2 | | | V | 200 ns; nonautomotive grade devices only | 7 |
| Common-Mode Transients | CMH, CML | -100 | | 100 | kV/µs | | 7 |
| AC Bipolar Voltage (max continuous working voltage) | | | | 565 | V peak | 50-year minimum lifetime | 7 |
| AC Unipolar Voltage (max continuous working voltage) | | | | 1131 | V peak | 50-year minimum lifetime | 7 |
| DC Voltage (max continuous working voltage) | | | | 1131 | V peak | 50-year minimum lifetime | 7 |
| IC Junction-to-Case Thermal Resistance, Side 1 | θJCI | | 46 | | °C/W | Thermocouple located at center of package underside | 5 |
| IC Junction-to-Case Thermal Resistance, Side 2 | θJCO | | 41 | | °C/W | Thermocouple located at center of package underside | 5 |
| IC Junction-to-Ambient Thermal Resistance | θJA | | 85 | | °C/W | Thermocouple located at center of package underside | 5 |
| Capacitance (Input-to-Output) | CI-O | | 1 | | pF | f = 1 MHz | 5 |
| Input Capacitance | CI | | 4 | | pF | | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | | limit = 5 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM3220/ADuM3221 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 | 5 |
## CAD (KiCad official)
- Symbol: `ADUM3221BRZ`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `adum3221brz-etched.step` / `adum3221brz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adum3221brz.step` / `adum3221brz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM3220_3221.pdf) (16 pp, sha256 `9d99041c90842985`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adum3221brz-datasheet.pdf)