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ADUM3201ARZ-RL7

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Analog Devices Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Contents

README

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ADUM3201ARZ-RL7

Analog Devices · Digital Isolators · SOIC-8

ADUM3201ARZ-RL7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, specified from 2.7 V to 5.5 V.
2 VOA output Logic Output A on the ADuM3201 pinout (side 1 output channel A).
3 VIB input Logic Input B on the ADuM3201 pinout (side 1 input channel B).
4 GND1 power_in Ground 1, the ground reference for isolator side 1.
5 GND2 power_in Ground 2, the ground reference for isolator side 2.
6 VOB output Logic Output B on the ADuM3201 pinout (side 2 output channel B).
7 VIA input Logic Input A on the ADuM3201 pinout (side 2 input channel A).
8 VDD2 power_in Supply voltage for isolator side 2, specified from 2.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature TA -40 105 °C 11
Supply Voltages VDD1, VDD2 2.7 5.5 V All voltages relative to their respective ground 11
Input Signal Rise and Fall Times 1 ms 11
Storage Temperature TST -55 150 °C 12
Ambient Operating Temperature TA -40 105 °C 12
Supply Voltages VDD1, VDD2 -0.5 7 V All voltages relative to their respective ground 12
Average Output Current, per Pin IO -35 35 mA Per pin; see Figure 3 for derating 12
Common-Mode Transients CMH, CML -100 100 kV/μs Across the insulation barrier 12
Input Supply Current, per Channel, Quiescent IDDI (Q) 0.4 0.8 mA 5 V operation 3
Output Supply Current, per Channel, Quiescent IDDO (Q) 0.5 0.6 mA 5 V operation 3
ADuM3201 VDD1 Supply Current, Quiescent, Two Channels IDD1 (Q) 1.1 1.5 mA 5 V operation; DC to 1 MHz logic signal freq. 3
ADuM3201 VDD2 Supply Current, Quiescent, Two Channels IDD2 (Q) 1.3 1.8 mA 5 V operation; DC to 1 MHz logic signal freq. 3
Input Currents IIA, IIB -10 0.01 10 μA 0 ≤ VIA, VIB ≤ VDD1 or VDD2 3
Logic Low Output Voltage VOAL 0 0.1 V 5 V operation; IOx = 20 μA, VIx = VIxL 3
Logic Low Output Voltage VOBL 0.04 0.1 V 5 V operation; IOx = 400 μA, VIx = VIxL 3
Logic Low Output Voltage 0.2 0.4 V 5 V operation; IOx = 4 mA, VIx = VIxL 3
Minimum Pulse Width, AR grade PW 1000 ns 5 V operation; CL = 15 pF, CMOS signal levels 3
Maximum Data Rate, AR grade 1 Mbps 5 V operation; CL = 15 pF, CMOS signal levels 3
Propagation Delay, AR grade tPHL, tPLH 20 150 ns 5 V operation; CL = 15 pF, CMOS signal levels 3
Pulse-Width Distortion, AR grade PWD 40 ns 5 V operation; CL = 15 pF, CMOS signal levels 3
Propagation Delay Skew, AR grade tPSK 100 ns 5 V operation; CL = 15 pF, CMOS signal levels 3
Channel-to-Channel Matching, AR grade tPSKCD/OD 50 ns 5 V operation; CL = 15 pF, CMOS signal levels 3
Output Rise/Fall Time (10% to 90%), AR grade tR/tF 10 ns 5 V operation; CL = 15 pF, CMOS signal levels 3
Common-Mode Transient Immunity at Logic High Output /CMH/ 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V 4
Common-Mode Transient Immunity at Logic Low Output /CML/ 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 4
Input Supply Current, per Channel, Quiescent IDDI (Q) 0.3 0.5 mA 3 V operation 5
Output Supply Current, per Channel, Quiescent IDDO (Q) 0.3 0.5 mA 3 V operation 5
ADuM3201 VDD1 Supply Current, Quiescent, Two Channels IDD1 (Q) 0.7 1.3 mA 3 V operation; DC to 1 MHz logic signal freq. 5
ADuM3201 VDD2 Supply Current, Quiescent, Two Channels IDD2 (Q) 0.8 1.6 mA 3 V operation; DC to 1 MHz logic signal freq. 5
Logic Low Input Threshold VIL 0.8 V 5 V/3 V operation 8
Logic Low Input Threshold VIL 0.4 V 3 V/5 V operation 8
Input Supply Current, per Channel, Quiescent IDDI (Q) 0.4 0.8 mA 5 V/3 V operation 7
Input Supply Current, per Channel, Quiescent IDDI (Q) 0.3 0.5 mA 3 V/5 V operation 7
Output Supply Current, per Channel, Quiescent IDDO (Q) 0.3 0.5 mA 5 V/3 V operation 7
Output Supply Current, per Channel, Quiescent IDDO (Q) 0.5 0.6 mA 3 V/5 V operation 7
ADuM3201 VDD1 Supply Current, Quiescent, Two Channels IDD1 (Q) 1.1 1.5 mA 5 V/3 V operation; DC to 1 MHz logic signal freq. 7
ADuM3201 VDD1 Supply Current, Quiescent, Two Channels IDD1 (Q) 0.7 1.3 mA 3 V/5 V operation; DC to 1 MHz logic signal freq. 7
ADuM3201 VDD2 Supply Current, Quiescent, Two Channels IDD2 (Q) 0.8 1.6 mA 5 V/3 V operation; DC to 1 MHz logic signal freq. 7
ADuM3201 VDD2 Supply Current, Quiescent, Two Channels IDD2 (Q) 1.3 1.8 mA 3 V/5 V operation; DC to 1 MHz logic signal freq. 7
Minimum Pulse Width, AR grade PW 1000 ns Mixed 5 V/3 V or 3 V/5 V operation; CL = 15 pF, CMOS signal levels 8
Maximum Data Rate, AR grade 1 Mbps Mixed 5 V/3 V or 3 V/5 V operation; CL = 15 pF, CMOS signal levels 8
Propagation Delay, AR grade tPHL, tPLH 15 150 ns Mixed 5 V/3 V or 3 V/5 V operation; CL = 15 pF, CMOS signal levels 8
Pulse-Width Distortion, AR grade PWD 40 ns Mixed 5 V/3 V or 3 V/5 V operation; CL = 15 pF, CMOS signal levels 8
Propagation Delay Skew, AR grade tPSK 50 ns Mixed 5 V/3 V or 3 V/5 V operation; CL = 15 pF, CMOS signal levels 8
Channel-to-Channel Matching, AR grade tPSKCD/OD 50 ns Mixed 5 V/3 V or 3 V/5 V operation; CL = 15 pF, CMOS signal levels 8
Output Rise/Fall Time (10% to 90%), AR grade tR/tF 10 ns Mixed 5 V/3 V or 3 V/5 V operation; CL = 15 pF, CMOS signal levels 8
Logic High Output Voltage VOAH 5 V 5 V operation; IOx = -20 μA, VIx = VIxH 3
Logic High Output Voltage VOBH 4.8 V 5 V operation; IOx = -4 mA, VIx = VIxH 3
Logic High Output Voltage VOAH 3 V 3 V operation; IOx = -20 μA, VIx = VIxH 5
Logic High Output Voltage VOBH 2.8 V 3 V operation; IOx = -4 mA, VIx = VIxH 5
Thermal Resistance, Junction-to-Case, Side 1 θJCI 46 °C/W Thermocouple located at center of package underside 10
Thermal Resistance, Junction-to-Case, Side 2 θJCO 41 °C/W 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN 60747-5-2, each ADuM320x is proof-tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC). 10

CAD (KiCad official)

  • Symbol: ADUM3201ARZ-RL7
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: adum3201arz-rl7-etched.step / adum3201arz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum3201arz-rl7.step / adum3201arz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (20 pp, sha256 89280283b903bd6b, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF