component

ADUM3150ARSZ

Public Made by Adom

by adom

Analog Devices Digital Isolators, SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232adum3150arszfactory-2.0.0extractor-text

Verified ADUM3150ARSZ

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADUM3150ARSZ · SSOP-20-208mil · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 21-page datasheet
  • ✓distributor: lcsc C660730, digikey 505-ADUM3150ARSZ-ND, mouser 584-ADUM3150ARSZ
  • ✓family: SSOP-20_5.3x7.2mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-04dlnc62/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ adum3150arsz.kicad_sym✓ adum3150arsz.kicad_mod✓ adum3150arsz.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10h ago
viewers adum3150arsz: viewers · Ray 10h ago
adum3150arsz-etched.glb Publish 0.1.0 · Ray 10h ago
adum3150arsz-etched.step adum3150arsz: factory component page (tier=mfr) · Ray 10h ago
adum3150arsz-hero.glb adum3150arsz: hero GLB from the etched model (keeps the MPN mark) · Ray 10h ago
adum3150arsz-hero.overlay.json Publish 0.1.0 · Ray 10h ago
adum3150arsz.glb Publish 0.1.0 · Ray 10h ago
adum3150arsz.kicad_mod Publish 0.1.0 · Ray 10h ago
adum3150arsz.kicad_sym Publish 0.1.0 · Ray 10h ago
adum3150arsz.lbr Publish 0.1.0 · Ray 10h ago
adum3150arsz.step Publish 0.1.0 · Ray 10h ago
package.json Publish 0.1.0 · Ray 10h ago
page.json Set visibility: public · Ray 10h ago
README.md Publish 0.1.0 · Ray 10h ago
verification.json Verified: Published by the parts factory: tier mfr, 20 pins · Ray 10h ago

ADUM3150ARSZ

Analog Devices · Digital Isolators · SSOP-20-208mil

ADUM3150ARSZ from Analog Devices, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Power supply for Side 1; a bypass capacitor from VDD1 to GND1 to local ground is required.
2 GND1 power_in Ground reference for isolator Side 1 (Ground 1).
3 MCLK input SPI clock input from the main controller.
4 MO input SPI data input from the main MO/SI line.
5 MI output SPI data output from the subordinate to the main MI/SO line.
6 MSS input Active-low subordinate select input from the main; may require as much as 10 ns setup time from the next clock or data edge, depending on speed grade.
7 VIA input Low speed data input A.
8 VOB output Low speed data output B.
9 DCLK output Delayed clock output providing a delayed copy of MCLK.
10 GND1 power_in Ground reference for isolator Side 1 (Ground 1).
11 GND2 power_in Ground reference for isolator Side 2 (Ground 2).
12 NIC unconnected No internal connection; not internally connected and serves no function in the ADuM3150.
13 VIB input Low speed data input B.
14 VOA output Low speed data output A.
15 SSS output Active-low subordinate select output to the subordinate.
16 SO input SPI data input from the subordinate to the main MI/SO line.
17 SI output SPI data output from the main to the subordinate MO/SI line.
18 SCLK output SPI clock output from the main controller.
19 GND2 power_in Ground reference for isolator Side 2 (Ground 2).
20 VDD2 power_in Power supply for Side 2; a bypass capacitor from VDD2 to GND2 to local ground is required.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SSOP-20-208mil
Category Communication Interface Chip/UART/485/232
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Range VDD1, VDD2 3 5.5 V 13
Operating Temperature Range TA -40 125 °C 13
Input Signal Rise/Fall Times 1 ms 13
Storage Temperature Range TST -65 150 °C 14
Ambient Operating Temperature Range TA -40 125 °C TA = 25°C unless otherwise noted 14
Supply Voltages VDD1, VDD2 -0.5 7 V 14
Input Voltages (VIA, VIB, MCLK, MO, SO, MSS) -0.5 V -0.5 V to VDDx + 0.5 V 14
Output Voltages (SCLK, DCLK, SSS, MI, SI, VOA, VOB) -0.5 V -0.5 V to VDDx + 0.5 V 14
Average Output Current per Pin -10 10 mA 14
Common-Mode Transients -100 100 kV/µs Across the insulation barrier 14
IC Junction-to-Case Thermal Resistance θJC 68.5 °C/W 4-layer JEDEC test board, JESD 51-7 specification 11
SPI Clock Rate (MCLK) SPIMCLK 10 MHz 5 V operation, A grade 3
Data Rate Fast (MO, SO) DRFAST 40 Mbps Within PWD limit; 5 V operation 3
Propagation Delay (MCLK, MO, SO) tPHL, tPLH 25 ns 50% input to 50% output; 5 V operation 3
Pulse Width (MCLK, MO, SO) PW 12.5 ns Within PWD limit; 5 V operation 3
Pulse Width Distortion (MCLK, MO, SO) PWD 2 ns /tPLH − tPHL/; 5 V operation 3
Codirectional Channel Matching tPSKCD 2 ns 5 V operation 3
Jitter, High Speed JHS 1 ns 5 V operation 3
Propagation Delay (MSS) tPHL, tPLH 21 25 ns 50% input to 50% output; 5 V operation 3
Pulse Width (MSS) PW 12.5 ns Within PWD limit; 5 V operation 3
Pulse Width Distortion (MSS) PWD 2 ns /tPLH − tPHL/; 5 V operation 3
Setup Time (MSS) MSSSETUP 1.5 ns 5 V operation 3
Propagation Delay (DCLK) tPHL, tPLH 50 ns tPMCLK + tPSO + 3 ns; 5 V operation 3
Pulse Width Distortion (DCLK) PWD 3 ns /tPLH − tPHL/; 5 V operation 3
Pulse Width (DCLK) PW 12 ns Within PWD limit; 5 V operation 3
Clock Delay Error DCLKERR 0 4.5 12 ns tPDCLK − (tPMCLK + tPSO); 5 V operation 3
Jitter (DCLK) JDCLK 1 ns 5 V operation 3
Data Rate Slow (VIA, VIB) DRSLOW 250 kbps Within PWD limit; 5 V operation 3
Propagation Delay (VIA, VIB) tPHL, tPLH 0.1 2.6 µs 50% input to 50% output; 5 V operation 3
Pulse Width (VIA, VIB) PW 4 µs Within PWD limit; 5 V operation 3
Jitter, Low Speed JLS 2.5 µs 5 V operation 3
VIx Minimum Input Skew tVIx SKEW 10 ns 5 V operation 3
Supply Current Side 1 IDD1 5 8.5 mA CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz; 5 V 3
Supply Current Side 2 IDD2 6.5 11 mA CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz; 5 V 4
Input Hysteresis VIHYST 500 mV 5 V operation 4
Input Current per Channel II -1 0.01 1 µA 0 V ≤ VINPUT ≤ VDDx 4
Output Voltage Logic High VOH 5 V IOUTPUT = −20 µA, VINPUT = VIH; min = VDDx − 0.1 4
Output Voltage Logic High VOH 4.8 V IOUTPUT = −4 mA, VINPUT = VIH; min = VDDx − 0.4 4
Output Voltage Logic Low VOL 0 0.1 V IOUTPUT = 20 µA, VINPUT = VIL 4
Output Voltage Logic Low VOL 0.2 0.4 V IOUTPUT = 4 mA, VINPUT = VIL 4
VDD1, VDD2 Undervoltage Lockout UVLO 2.6 V 4
Dynamic Input Supply Current, High Speed Channel IDDI(D) 0.08 mA/Mbps 5 V operation 4
Dynamic Output Supply Current, High Speed Channel IDDO(D) 0.046 mA/Mbps 5 V operation 4
Quiescent Side 1 Current IDD1(Q) 4.4 mA All low speed channels; 5 V 4
Quiescent Side 2 Current IDD2(Q) 6.1 mA All low speed channels; 5 V 4
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% 4
Common-Mode Transient Immunity /CM/ 25 35 kV/µs VINPUT = VDDx, VCM = 1000 V, Transient magnitude = 800 V 4
SPI Clock Rate (MCLK) SPIMCLK 8.3 MHz 3.3 V operation, A grade 5
Propagation Delay (MCLK, MO, SO) tPHL, tPLH 30 ns 50% input to 50% output; 3.3 V operation 5
Clock Delay Error DCLKERR -4 2.4 9 ns tPDCLK − (tPMCLK + tPSO); 3.3 V operation 5
Supply Current Side 1 IDD1 3.5 6 mA CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz; 3.3 V 5
Supply Current Side 2 IDD2 4.9 8 mA CL = 0 pF, DRFAST = 1 MHz, DRSLOW = 0 MHz; 3.3 V 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN IEC 60747-17 (VDE 0884-17), the ADuM3150 is proof tested by applying an insulation test voltage ≥ 1059 V peak for 1 second (partial discharge detection limit = 5 pC). 11

CAD (KiCad official)

  • Symbol: ADUM3150ARSZ
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: adum3150arsz-etched.step / adum3150arsz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum3150arsz.step / adum3150arsz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (21 pp, sha256 ff06825b7c55df86, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF