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ADUM250N0BRIZ

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Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232adum250n0brizfactory-2.0.0extractor-text

Verified ADUM250N0BRIZ

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADUM250N0BRIZ · SOIC-16-300mil · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 22-page datasheet
  • ✓distributor: lcsc C660696, digikey 505-ADUM250N0BRIZ-ND, mouser 584-ADUM250N0BRIZ
  • ✓family: SOIC-16W_7.5x12.8mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-w4_bf8uo/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.22)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ adum250n0briz.kicad_sym✓ adum250n0briz.kicad_mod✓ adum250n0briz.step
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ADUM250N0BRIZ

Analog Devices · Digital Isolators · SOIC-16-300mil

ADUM250N0BRIZ from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, with a recommended operating range of 1.7 V to 5.5 V.
2 VIA input Logic input A on side 1; logic high requires at least 0.7 × VDD1 and logic low at most 0.3 × VDD1, with absolute maximum −0.5 V to VDD1 + 0.5 V.
3 VIB input Logic input B on side 1; logic high requires at least 0.7 × VDD1 and logic low at most 0.3 × VDD1, with absolute maximum −0.5 V to VDD1 + 0.5 V.
4 VIC input Logic input C on side 1; logic high requires at least 0.7 × VDD1 and logic low at most 0.3 × VDD1, with absolute maximum −0.5 V to VDD1 + 0.5 V.
5 VID input Logic input D on side 1; logic high requires at least 0.7 × VDD1 and logic low at most 0.3 × VDD1, with absolute maximum −0.5 V to VDD1 + 0.5 V.
6 VIE input Logic input E on side 1; logic high requires at least 0.7 × VDD1 and logic low at most 0.3 × VDD1, with absolute maximum −0.5 V to VDD1 + 0.5 V.
7 NIC unconnected No internal connection; leave this pin floating.
8 GND1 power_in Ground reference for isolator side 1.
9 GND2 power_in Ground reference for isolator side 2.
10 NIC unconnected No internal connection; leave this pin floating.
11 VOE output Logic output E on side 2; absolute maximum range is −0.5 V to VDD2 + 0.5 V and average output current is limited to −10 mA to +10 mA per pin.
12 VOD output Logic output D on side 2; absolute maximum range is −0.5 V to VDD2 + 0.5 V and average output current is limited to −10 mA to +10 mA per pin.
13 VOC output Logic output C on side 2; absolute maximum range is −0.5 V to VDD2 + 0.5 V and average output current is limited to −10 mA to +10 mA per pin.
14 VOB output Logic output B on side 2; absolute maximum range is −0.5 V to VDD2 + 0.5 V and average output current is limited to −10 mA to +10 mA per pin.
15 VOA output Logic output A on side 2; absolute maximum range is −0.5 V to VDD2 + 0.5 V and average output current is limited to −10 mA to +10 mA per pin.
16 VDD2 power_in Supply voltage for isolator side 2, with a recommended operating range of 1.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Pulse width PW 6.6 ns Within PWD limit 3
Data rate 150 Mbps Within PWD limit 3
Input current per channel II -10 0.01 10 µA 0 V ≤ VIx ≤ VDDx 3
Common-mode transient immunity, high /CMH/ 75 100 kV/µs VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V 3
Common-mode transient immunity, low /CML/ 75 100 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 3
Propagation delay (5 V) tPHL, tPLH 4.8 7.2 13 ns 50% input to 50% output 3
Pulse width distortion (5 V) PWD 0.5 4.5 ns /tPLH − tPHL/ 3
Propagation delay skew (5 V) tPSK 6.1 ns Between any two units at the same temperature, voltage, and load 3
Channel matching codirectional (5 V) tPSKCD 0.5 4 ns Codirectional 3
Channel matching opposing direction (5 V) tPSKOD 0.5 4.5 ns Opposing direction 3
Quiescent supply current side 1 (5 V) IDD1 (Q) 2.54 3.7 mA VI5 = 0 (N0) 3
Quiescent supply current side 2 (5 V) IDD2 (Q) 3.34 4.56 mA VI5 = 0 (N0) 3
Quiescent supply current side 1 (5 V) IDD1 (Q) 16.8 27.5 mA VI5 = 1 (N0) 3
Quiescent supply current side 2 (5 V) IDD2 (Q) 3.57 4.9 mA VI5 = 1 (N0) 3
Logic low output voltage (5 V) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 3
Logic low output voltage (5 V) VOL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 3
Propagation delay (3.3 V) tPHL, tPLH 4.8 6.8 14 ns 50% input to 50% output 5
Pulse width distortion (3.3 V) PWD 0.7 4.5 ns /tPLH − tPHL/ 5
Propagation delay skew (3.3 V) tPSK 7.5 ns Between any two units at the same temperature, voltage, and load 5
Channel matching codirectional (3.3 V) tPSKCD 0.7 4 ns Codirectional 5
Channel matching opposing direction (3.3 V) tPSKOD 0.7 4.5 ns Opposing direction 5
Quiescent supply current side 1 (3.3 V) IDD1 (Q) 2.36 3.52 mA VI5 = 0 (N0) 5
Quiescent supply current side 2 (3.3 V) IDD2 (Q) 3.2 4.42 mA VI5 = 0 (N0) 5
Quiescent supply current side 1 (3.3 V) IDD1 (Q) 16.5 27.2 mA VI5 = 1 (N0) 5
Quiescent supply current side 2 (3.3 V) IDD2 (Q) 3.43 4.76 mA VI5 = 1 (N0) 5
Logic low output voltage (3.3 V) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 5
Logic low output voltage (3.3 V) VOL 0.2 0.4 V IOx = 2 mA, VIx = VIxL 5
Propagation delay (2.5 V) tPHL, tPLH 5 7 14 ns 50% input to 50% output 7
Pulse width distortion (2.5 V) PWD 0.7 5 ns /tPLH − tPHL/ 7
Propagation delay skew (2.5 V) tPSK 6.8 ns Between any two units at the same temperature, voltage, and load 7
Channel matching codirectional (2.5 V) tPSKCD 0.7 5 ns Codirectional 7
Channel matching opposing direction (2.5 V) tPSKOD 0.7 5 ns Opposing direction 7
Quiescent supply current side 1 (2.5 V) IDD1 (Q) 2.28 3.44 mA VI5 = 0 (N0) 7
Quiescent supply current side 2 (2.5 V) IDD2 (Q) 3.13 4.35 mA VI5 = 0 (N0) 7
Quiescent supply current side 1 (2.5 V) IDD1 (Q) 16.4 27.1 mA VI5 = 1 (N0) 7
Quiescent supply current side 2 (2.5 V) IDD2 (Q) 3.34 4.67 mA VI5 = 1 (N0) 7
Logic low output voltage (2.5 V) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 7
Logic low output voltage (2.5 V) VOL 0.2 0.4 V IOx = 2 mA, VIx = VIxL 7
Propagation delay (1.8 V) tPHL, tPLH 5.8 8.7 15 ns 50% input to 50% output 9
Pulse width distortion (1.8 V) PWD 0.7 5 ns /tPLH − tPHL/ 9
Propagation delay skew (1.8 V) tPSK 7 ns Between any two units at the same temperature, voltage, and load 9
Channel matching codirectional (1.8 V) tPSKCD 0.7 5 ns Codirectional 9
Channel matching opposing direction (1.8 V) tPSKOD 0.7 5 ns Opposing direction 9
Quiescent supply current side 1 (1.8 V) IDD1 (Q) 2.19 3.35 mA VI5 = 0 (N0) 9
Quiescent supply current side 2 (1.8 V) IDD2 (Q) 3.07 4.29 mA VI5 = 0 (N0) 9
Quiescent supply current side 1 (1.8 V) IDD1 (Q) 16.3 27 mA VI5 = 1 (N0) 9
Quiescent supply current side 2 (1.8 V) IDD2 (Q) 3.28 4.61 mA VI5 = 1 (N0) 9
Logic low output voltage (1.8 V) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 9
Logic low output voltage (1.8 V) VOL 0.2 0.4 V IOx = 2 mA, VIx = VIxL 9
Operating temperature range TA -40 125 °C 12
Supply voltage range VDD1, VDD2 1.7 5.5 V 12
Input signal rise and fall times 1 ms 12
Storage temperature range TST -65 150 °C 13
Ambient operating temperature range TA -40 125 °C 13
Supply voltages VDD1, VDD2 -0.5 7 V 13
Average output current per pin, side 1 IO1 -10 10 mA See Figure 4 for derating 13
Average output current per pin, side 2 IO2 -10 10 mA See Figure 4 for derating 13
Common-mode transients -150 150 kV/µs Refers to common-mode transients across the insulation barrier 13
IC junction to ambient thermal resistance θJA 45 °C/W Thermocouple located at center of package underside 11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC 6000 V rms for 1 sec. 2 In accordance with DIN V VDE V 0884-10, each ADuM250N/ADuM251N/ADuM252N in the RI-16 wide-body (SOIC_IC) package is proof tested by applying an insulation test voltage ≥ 1592 V 11

CAD (KiCad official)

  • Symbol: ADUM250N0BRIZ
  • Footprint: Package_SO:SOIC-16W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: adum250n0briz-etched.step / adum250n0briz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum250n0briz.step / adum250n0briz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (22 pp, sha256 0d00e5889d71380c, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF