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ADUM2402BRWZ-RL

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Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADUM2402BRWZ-RL

Analog Devices · Digital Isolators · SOIC-16-300mil

ADUM2402BRWZ-RL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, 2.7 V to 5.5 V.
2 GND1 power_in Ground 1, the ground reference for isolator side 1; internally connected to pin 8, and connecting both to GND1 is recommended.
3 VIA input Logic input A on isolator side 1, driving output VOA on side 2.
4 VIB input Logic input B on isolator side 1, driving output VOB on side 2.
5 VOC output Logic output C on isolator side 1; enabled when VE1 is high or disconnected and disabled (high impedance) when VE1 is low.
6 VOD output Logic output D on isolator side 1; enabled when VE1 is high or disconnected and disabled (high impedance) when VE1 is low.
7 VE1 input Output enable 1, active-high logic input for VOC and VOD; connecting it to an external logic high or low is recommended in noisy environments.
8 GND1 power_in Ground 1, the ground reference for isolator side 1; internally connected to pin 2, and connecting both to GND1 is recommended.
9 GND2 power_in Ground 2, the ground reference for isolator side 2; internally connected to pin 15, and connecting both to GND2 is recommended.
10 VE2 input Output enable 2, active-high logic input for VOA and VOB; outputs are enabled when high or disconnected and disabled when low, and connecting it to an external logic high or low is recommended in noisy environments.
11 VID input Logic input D on isolator side 2, driving output VOD on side 1.
12 VIC input Logic input C on isolator side 2, driving output VOC on side 1.
13 VOB output Logic output B on isolator side 2; enabled when VE2 is high or disconnected and disabled when VE2 is low.
14 VOA output Logic output A on isolator side 2; enabled when VE2 is high or disconnected and disabled when VE2 is low.
15 GND2 power_in Ground 2, the ground reference for isolator side 2; internally connected to pin 9, and connecting both to GND2 is recommended.
16 VDD2 power_in Supply voltage for isolator side 2, 2.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Logic High Input Threshold (5 V operation) VIH, VEH 2 V 3
Logic Low Input Threshold (5 V operation) VIL, VEL 0.8 V 3
Input Currents (5 V operation) IIA, IIB, IIC, IID, IE1, IE2 -10 0.01 10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 3
Input Supply Current per Channel, Quiescent (5 V operation) IDDI (Q) 0.5 0.53 mA 3
Output Supply Current per Channel, Quiescent (5 V operation) IDDO (Q) 0.19 0.21 mA 3
ADuM2402 VDD1 or VDD2 Supply Current, DC to 2 Mbps (5 V operation) IDD1 (Q), IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal frequency 3
ADuM2402 VDD1 or VDD2 Supply Current, 10 Mbps (5 V operation) IDD1 (10), IDD2 (10) 5.6 7 mA 5 MHz logic signal frequency 3
Logic High Output Voltage VOAH, VOBH (5 V operation) VOAH, VOBH 5 V IOx = −20 μA, VIx = VIxH; min is (VDD1 or VDD2) − 0.1 3
Logic High Output Voltage VOCH, VODH (5 V operation) VOCH, VODH 4.8 V IOx = −4 mA, VIx = VIxH; min is (VDD1 or VDD2) − 0.4 3
Logic Low Output Voltage (5 V operation) VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 μA, VIx = VIxL 3
Logic Low Output Voltage (5 V operation) VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 3
Logic Low Output Voltage (5 V operation) VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 3
Minimum Pulse Width (BRWZ, 5 V operation) PW 100 ns CL = 15 pF, CMOS signal levels 4
Maximum Data Rate (BRWZ, 5 V operation) 10 Mbps CL = 15 pF, CMOS signal levels 4
Propagation Delay (BRWZ, 5 V operation) tPHL, tPLH 20 32 50 ns CL = 15 pF, CMOS signal levels 4
Pulse Width Distortion (BRWZ, 5 V operation) PWD 3 ns CL = 15 pF, CMOS signal levels 4
Propagation Delay Skew (BRWZ, 5 V operation) tPSK 15 ns CL = 15 pF, CMOS signal levels 4
Channel-to-Channel Matching, Codirectional Channels (BRWZ, 5 V operation) tPSKCD 3 ns CL = 15 pF, CMOS signal levels 4
Channel-to-Channel Matching, Opposing-Directional Channels (BRWZ, 5 V operation) tPSKOD 6 ns CL = 15 pF, CMOS signal levels 4
Output Disable Propagation Delay (High/Low to High Impedance, 5 V operation) tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels 4
Output Enable Propagation Delay (High Impedance to High/Low, 5 V operation) tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels 4
Output Rise/Fall Time (10% to 90%) (5 V operation) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels 4
Common-Mode Transient Immunity at Logic High Output (5 V operation) /CMH/ 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 4
Common-Mode Transient Immunity at Logic Low Output (5 V operation) /CML/ 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 4
Logic High Input Threshold (3 V operation) VIH, VEH 1.6 V 5
Logic Low Input Threshold (3 V operation) VIL, VEL 0.4 V 5
Input Supply Current per Channel, Quiescent (3 V operation) IDDI (Q) 0.26 0.31 mA 5
Output Supply Current per Channel, Quiescent (3 V operation) IDDO (Q) 0.11 0.14 mA 5
ADuM2402 VDD1 or VDD2 Supply Current, DC to 2 Mbps (3 V operation) IDD1 (Q), IDD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal frequency 5
ADuM2402 VDD1 or VDD2 Supply Current, 10 Mbps (3 V operation) IDD1 (10), IDD2 (10) 3 4.2 mA 5 MHz logic signal frequency 5
Logic High Output Voltage VOAH, VOBH (3 V operation) VOAH, VOBH 3 V IOx = −20 μA, VIx = VIxH; min is (VDD1 or VDD2) − 0.1 5
Logic High Output Voltage VOCH, VODH (3 V operation) VOCH, VODH 2.8 V IOx = −4 mA, VIx = VIxH; min is (VDD1 or VDD2) − 0.4 5
Logic Low Output Voltage (3 V operation) VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 μA, VIx = VIxL 5
Logic Low Output Voltage (3 V operation) VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 5
Logic Low Output Voltage (3 V operation) VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 5
Minimum Pulse Width (BRWZ, 3 V operation) PW 100 ns CL = 15 pF, CMOS signal levels 6
Maximum Data Rate (BRWZ, 3 V operation) 10 Mbps CL = 15 pF, CMOS signal levels 6
Propagation Delay (BRWZ, 3 V operation) tPHL, tPLH 20 38 50 ns CL = 15 pF, CMOS signal levels 6
Pulse Width Distortion (BRWZ, 3 V operation) PWD 3 ns CL = 15 pF, CMOS signal levels 6
Propagation Delay Skew (BRWZ, 3 V operation) tPSK 22 ns CL = 15 pF, CMOS signal levels 6
Channel-to-Channel Matching, Codirectional Channels (BRWZ, 3 V operation) tPSKCD 3 ns CL = 15 pF, CMOS signal levels 6
Channel-to-Channel Matching, Opposing-Directional Channels (BRWZ, 3 V operation) tPSKOD 6 ns CL = 15 pF, CMOS signal levels 6
Output Disable Propagation Delay (High/Low to High Impedance, 3 V operation) tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels 6
Output Enable Propagation Delay (High Impedance to High/Low, 3 V operation) tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels 6
Output Rise/Fall Time (10% to 90%) (3 V operation) tR/tF 3 ns CL = 15 pF, CMOS signal levels 6
Common-Mode Transient Immunity at Logic High Output (3 V operation) /CMH/ 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 6
Common-Mode Transient Immunity at Logic Low Output (3 V operation) /CML/ 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 6
Operating Temperature (TA) TA -40 105 °C 11
Supply Voltages (VDD1, VDD2) VDD1, VDD2 2.7 5.5 V All voltages are relative to their respective ground 11
Input Signal Rise and Fall Times 1 ms 11
Storage Temperature Range TST -65 150 °C 12
Ambient Operating Temperature Range TA -40 105 °C 12
Supply Voltage Range VDD1, VDD2 -0.5 7 V All voltages are relative to their respective ground 12
Input Voltage Range VIA, VIB, VIC, VID, VE1, VE2 -0.5 V Maximum is VDDI + 0.5 V 12
Output Voltage Range VOA, VOB, VOC, VOD -0.5 V Maximum is VDDO + 0.5 V 12
Average Output Current Per Pin, Side 1 IO1 -18 18 mA 12
Average Output Current Per Pin, Side 2 IO2 -22 22 mA 12
Common-Mode Transients -100 100 kV/μs Refers to common-mode transients across the insulation barrier 12
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located at center of package underside 10
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W Thermocouple located at center of package underside 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-10, each ADuM240x is proof tested by applying an insulation test voltage ≥1590 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on 10

CAD (KiCad official)

  • Symbol: ADUM2402BRWZ-RL
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: adum2402brwz-rl-etched.step / adum2402brwz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum2402brwz-rl.step / adum2402brwz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 e555661788bf184a, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF