Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

ADUM150N1BRZ

Analog Devices · Digital Isolators · SOIC-16

ADUM150N1BRZ from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, operating range 1.7 V to 5.5 V.
2 VIA input Logic input A.
3 VIB input Logic input B.
4 VIC input Logic input C.
5 VID input Logic input D.
6 VIE input Logic input E.
7 NIC unconnected No internal connection; leave this pin floating.
8 GND1 power_in Ground 1, ground reference for isolator side 1.
9 GND2 power_in Ground 2, ground reference for isolator side 2.
10 NIC unconnected No internal connection; leave this pin floating.
11 VOE output Logic output E.
12 VOD output Logic output D.
13 VOC output Logic output C.
14 VOB output Logic output B.
15 VOA output Logic output A.
16 VDD2 power_in Supply voltage for isolator side 2, operating range 1.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Propagation Delay (5 V) tPHL, tPLH 4.8 7.2 13 ns 50% input to 50% output, 4.5 V to 5.5 V 4
Pulse Width Distortion (5 V) PWD 0.5 4.5 ns /tPLH − tPHL/ 4
Propagation Delay Skew (5 V) tPSK 6.1 ns Between any two units at the same temperature, voltage, and load 4
Channel Matching Codirectional (5 V) tPSKCD 0.5 4 ns 4
Channel Matching Opposing Direction (5 V) tPSKOD 0.5 4.5 ns 4
Pulse Width (5 V) PW 6.6 ns Within pulse width distortion (PWD) limit 4
Data Rate (5 V) 150 Mbps Within PWD limit 4
Output Voltage Logic Low (5 V) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 4
Output Voltage Logic Low (5 V) VOL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 4
Input Current per Channel II -10 0.01 10 µA 0 V ≤ VIx ≤ VDDx 4
Quiescent Supply Current Side 1, ADuM150N (5 V) IDD1 (Q) 2.54 3.7 mA VI = 1 (N1) 4
Quiescent Supply Current Side 2, ADuM150N (5 V) IDD2 (Q) 3.34 4.56 mA VI = 1 (N1) 4
Quiescent Supply Current Side 1, ADuM150N (5 V) IDD1 (Q) 16.8 27.5 mA VI = 0 (N1) 4
Quiescent Supply Current Side 2, ADuM150N (5 V) IDD2 (Q) 3.57 4.9 mA VI = 0 (N1) 4
Common-Mode Transient Immunity High /CMH/ 75 100 kV/µs VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V 5
Common-Mode Transient Immunity Low /CML/ 75 100 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 5
Propagation Delay (3.3 V) tPHL, tPLH 4.8 6.8 14 ns 50% input to 50% output, 3.0 V to 3.6 V 5
Pulse Width Distortion (3.3 V) PWD 0.7 4.5 ns /tPLH − tPHL/ 5
Propagation Delay Skew (3.3 V) tPSK 7.5 ns Between any two units at the same temperature, voltage, and load 6
Quiescent Supply Current Side 1, ADuM150N (3.3 V) IDD1 (Q) 2.36 3.52 mA VI = 1 (N1) 6
Quiescent Supply Current Side 2, ADuM150N (3.3 V) IDD2 (Q) 3.2 4.42 mA VI = 1 (N1) 6
Quiescent Supply Current Side 1, ADuM150N (3.3 V) IDD1 (Q) 16.5 27.2 mA VI = 0 (N1) 6
Quiescent Supply Current Side 2, ADuM150N (3.3 V) IDD2 (Q) 3.43 4.76 mA VI = 0 (N1) 6
Propagation Delay (2.5 V) tPHL, tPLH 5 7 14 ns 50% input to 50% output, 2.25 V to 2.75 V 7
Pulse Width Distortion (2.5 V) PWD 0.7 5 ns /tPLH − tPHL/ 7
Propagation Delay Skew (2.5 V) tPSK 6.8 ns Between any two units at the same temperature, voltage, load 7
Quiescent Supply Current Side 1, ADuM150N (2.5 V) IDD1 (Q) 2.28 3.44 mA VI = 1 (N1) 8
Quiescent Supply Current Side 2, ADuM150N (2.5 V) IDD2 (Q) 3.13 4.35 mA VI = 1 (N1) 8
Quiescent Supply Current Side 1, ADuM150N (2.5 V) IDD1 (Q) 16.4 27.1 mA VI = 0 (N1) 8
Quiescent Supply Current Side 2, ADuM150N (2.5 V) IDD2 (Q) 3.34 4.67 mA VI = 0 (N1) 8
Propagation Delay (1.8 V) tPHL, tPLH 5.8 8.7 15 ns 50% input to 50% output, 1.7 V to 1.9 V 9
Pulse Width Distortion (1.8 V) PWD 0.7 5 ns /tPLH − tPHL/ 9
Propagation Delay Skew (1.8 V) tPSK 7 ns Between any two units at the same temperature, voltage, and load 9
Quiescent Supply Current Side 1, ADuM150N (1.8 V) IDD1 (Q) 2.19 3.35 mA VI = 1 (N1) 9
Quiescent Supply Current Side 2, ADuM150N (1.8 V) IDD2 (Q) 3.07 4.29 mA VI = 1 (N1) 9
Quiescent Supply Current Side 1, ADuM150N (1.8 V) IDD1 (Q) 16.3 27 mA VI = 0 (N1) 9
Quiescent Supply Current Side 2, ADuM150N (1.8 V) IDD2 (Q) 3.28 4.61 mA VI = 0 (N1) 9
Supply Voltages VDD1, VDD2 1.7 5.5 V 13
Operating Temperature TA -40 125 °C 13
Input Signal Rise and Fall Times 1 ms 13
Storage Temperature TST -65 150 °C TA = 25°C 14
Ambient Operating Temperature TA -40 125 °C TA = 25°C 14
Supply Voltages VDD1, VDD2 -0.5 7 V TA = 25°C 14
Input Voltages VIA-VIE -0.5 V Max is VDDI + 0.5 V 14
Output Voltages VOA-VOE -0.5 V Max is VDDO + 0.5 V 14
Side 1 Average Output Current per Pin IO1 -10 10 mA 14
Side 2 Average Output Current per Pin IO2 -10 10 mA 14
Common-Mode Transients -150 150 kV/µs Across the insulation barrier 14
IC Junction to Ambient Thermal Resistance θJA 75 °C/W Thermocouple located at center of package underside 11
Rated Dielectric Insulation Voltage 3000 V rms 1-minute duration 11
Capacitance (Input to Output) CI-O 2.2 pF f = 1 MHz 11
Input Capacitance CI 4 pF 11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM150N/ADuM151N/ADuM152N in the R-16 narrow-body (SOIC_N) package is proof tested by applying an insulation test voltage ≥ 1059 V peak for 12

CAD (KiCad official)

  • Symbol: ADUM150N1BRZ
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: adum150n1brz-etched.step / adum150n1brz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum150n1brz.step / adum150n1brz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (21 pp, sha256 b310779f78355b9e, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF