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ADUM142D0BRZ

Analog Devices · Digital Isolators · SOIC-16

ADUM142D0BRZ from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1 (devices operate with supply on either side from 1.8 V to 5 V).
2 GND1 power_in Ground reference for isolator side 1.
3 VIA input Logic input A.
4 VIB input Logic input B.
5 VOC output Logic output C.
6 VOD output Logic output D.
7 DISABLE1 input Input disable 1; disables the isolator inputs, and outputs take the logic state set by the fail-safe option in the Ordering Guide.
8 GND1 power_in Ground reference for isolator side 1.
9 GND2 power_in Ground reference for isolator side 2.
10 DISABLE2 input Input disable 2; disables the isolator inputs, and outputs take the logic state set by the fail-safe option in the Ordering Guide.
11 VID input Logic input D.
12 VIC input Logic input C.
13 VOB output Logic output B.
14 VOA output Logic output A.
15 GND2 power_in Ground reference for isolator side 2.
16 VDD2 power_in Supply voltage for isolator side 2 (devices operate with supply on either side from 1.8 V to 5 V).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Propagation Delay tPHL, tPLH 4.8 7.2 13 ns 50% input to 50% output, 5 V 4
Pulse Width Distortion PWD 0.5 3 ns /tPLH − tPHL/, 5 V 4
Propagation Delay Skew tPSK 6.1 ns Between any two units at the same temperature, voltage, and load, 5 V 4
Channel Matching Codirectional tPSKCD 0.5 3 ns 5 V 4
Channel Matching Opposing Direction tPSKOD 0.5 3 ns 5 V 4
Pulse Width PW 6.6 ns Within pulse width distortion (PWD) limit, 5 V 4
Data Rate 150 Mbps Within PWD limit, 5 V 4
Output Voltage Logic Low VOL 0 0.1 V IOx = 20 µA, VIx = VIxL, 5 V 4
Output Voltage Logic Low VOL 0.2 0.4 V IOx = 4 mA, VIx = VIxL, 5 V 4
Input Current per Channel II -10 0.01 10 µA 0 V ≤ VIx ≤ VDDx 4
VE2 Enable Input Pull-Up Current IPU -10 -3 µA VE2 = 0 V 4
DISABLE1 Input Pull-Down Current IPD 9 15 µA DISABLE1 = VDDx 4
Tristate Output Current per Channel IOZ -10 0.01 10 µA 0 V ≤ VOx ≤ VDDx 4
Quiescent Supply Current Side 1 IDD1 (Q) 1.6 2.46 mA ADuM142D, VI = 0 (D0), 5 V 4
Quiescent Supply Current Side 2 IDD2 (Q) 1.6 2.46 mA ADuM142D, VI = 0 (D0), 5 V 4
Quiescent Supply Current Side 1 IDD1 (Q) 7.2 11.5 mA ADuM142D, VI = 1 (D0), 5 V 4
Quiescent Supply Current Side 2 IDD2 (Q) 8.4 11.5 mA ADuM142D, VI = 1 (D0), 5 V 5
Common-Mode Transient Immunity High /CMH/ 75 100 kV/µs VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V 5
Common-Mode Transient Immunity Low /CML/ 75 100 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 5
Supply Current Side 1, 1 Mbps IDD1 4.3 7.7 mA ADuM142D, 1 Mbps, 5 V 5
Supply Current Side 2, 1 Mbps IDD2 5.3 8.7 mA ADuM142D, 1 Mbps, 5 V 5
Supply Current Side 1, 25 Mbps IDD1 6 9.3 mA ADuM142D, 25 Mbps, 5 V 5
Supply Current Side 2, 25 Mbps IDD2 6.7 10.1 mA ADuM142D, 25 Mbps, 5 V 5
Supply Current Side 1, 100 Mbps IDD1 10.3 14.2 mA ADuM142D, 100 Mbps, 5 V 5
Supply Current Side 2, 100 Mbps IDD2 11 14.9 mA ADuM142D, 100 Mbps, 5 V 5
Propagation Delay tPHL, tPLH 4.8 6.8 14 ns 50% input to 50% output, 3.3 V 6
Propagation Delay tPHL, tPLH 5 7 14 ns 50% input to 50% output, 2.5 V 8
Propagation Delay tPHL, tPLH 5.8 8.7 15 ns 50% input to 50% output, 1.8 V 10
Supply Voltage VDD1, VDD2 1.7 5.5 V 17
Operating Temperature TA -40 125 °C 17
Input Signal Rise and Fall Times 1 ms 17
Supply Voltages VDD1, VDD2 -0.5 7 V TA = 25°C 18
Input Voltages VIA, VIB, VIC, VID, VE1, VE2, DISABLE1, DISABLE2 -0.5 V Maximum is VDDI + 0.5 V 18
Output Voltages VOA, VOB, VOC, VOD -0.5 V Maximum is VDDO + 0.5 V 18
Side 1 Output Current IO1 -10 10 mA Average output current per pin 18
Side 2 Output Current IO2 -10 10 mA Average output current per pin 18
Common-Mode Transients -150 150 kV/µs Across the insulation barrier 18
Storage Temperature Range TST -65 150 °C 18
Ambient Operating Temperature Range TA -40 125 °C 18
Maximum Fault Junction Temperature per DIN V VDE V 0884-11 TJ 150 °C 18
Maximum Fault Junction Temperature per Mold Compound TJ 300 °C 18
Maximum Continuous Working Voltage, AC bipolar 565 V peak Reinforced insulation per DIN EN IEC 60747-17 (VDE 0884-17) 18
Junction to Ambient Thermal Resistance, R-16 SOIC_N θJA 76 °C/W Thermocouple located at center of package underside 13
Rated Dielectric Insulation Voltage, R-16 3000 V rms 1-minute duration 12
Minimum External Air Gap (Clearance), R-16 L (I01) 4 mm Measured from input terminals to output terminals, shortest distance through air 12
Minimum External Tracking (Creepage), R-16 L (I02) 4 mm Measured from input terminals to output terminals, shortest distance path along body 12
Capacitance (Input to Output) CI-O 2.2 pF f = 1 MHz 13
Input Capacitance CI 4 pF 13
Change vs. Temperature of PWD 1.5 ps/°C 5 V 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E in the R-16 narrow body [SOIC_N] package is proof tested by applying an insulation test 14

CAD (KiCad official)

  • Symbol: ADUM142D0BRZ
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: adum142d0brz-etched.step / adum142d0brz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum142d0brz.step / adum142d0brz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (31 pp, sha256 d8dc27340f57bada, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF