component
ADUM141E0BRZ
Public Made by Adomby adom
Analog Devices Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownADUM141E0BRZ
Analog Devices · Digital Isolators · SOIC-16
ADUM141E0BRZ from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, which the datasheet states can range from 1.8 V to 5 V, with a recommended 0.01 µF to 0.1 µF bypass capacitor between Pin 1 and Pin 2. |
| 2 | GND1 | power_in | Ground reference for isolator side 1; Pin 2 and Pin 8 are both side-1 ground connections. |
| 3 | VIA | input | Logic input A on isolator side 1. |
| 4 | VIB | input | Logic input B on isolator side 1. |
| 5 | VIC | input | Logic input C on isolator side 1. |
| 6 | VOD | output | Logic output D on isolator side 1, enabled when VE1 is high or disconnected and set to high-impedance when VE1 is low. |
| 7 | VE1 | input | Output Enable 1, an active high logic input that enables the VOD output when high or disconnected and disables VOD to the high-Z state when low. |
| 8 | GND1 | power_in | Ground reference for isolator side 1; grouped with Pin 2 as the side-1 ground pair. |
| 9 | GND2 | power_in | Ground reference for isolator side 2; Pin 9 and Pin 15 are both side-2 ground connections. |
| 10 | VE2 | input | Output Enable 2, an active high logic input that enables the VOA, VOB and VOC outputs when high or disconnected and disables them to the high-Z state when low. |
| 11 | VID | input | Logic input D on isolator side 2. |
| 12 | VOC | output | Logic output C on isolator side 2, enabled by VE2 and set to high-impedance when VE2 is low. |
| 13 | VOB | output | Logic output B on isolator side 2, enabled by VE2 and set to high-impedance when VE2 is low. |
| 14 | VOA | output | Logic output A on isolator side 2, enabled by VE2 and set to high-impedance when VE2 is low. |
| 15 | GND2 | power_in | Ground reference for isolator side 2; grouped with Pin 9 as the side-2 ground pair. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, which the datasheet states can range from 1.8 V to 5 V, with bypass recommended between Pin 15 and Pin 16. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-16 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature | TA | -40 | 125 | °C | 17 | ||
| Supply Voltages | VDD1, VDD2 | 1.7 | 5.5 | V | 17 | ||
| Storage Temperature (TST) Range | TST | -65 | 150 | °C | 18 | ||
| Ambient Operating Temperature (TA) Range | TA | -40 | 125 | °C | 18 | ||
| Maximum Fault Junction Temperature (TJ) | TJ | 150 | °C | per DIN V VDE V 0884-11 | 18 | ||
| Maximum Fault Junction Temperature (TJ) | TJ | 300 | °C | per Mold Compound | 18 | ||
| Supply Voltages (VDD1, VDD2) | VDD1, VDD2 | -0.5 | 7 | V | 18 | ||
| Input Voltages (max = VDDI1 + 0.5 V) | VIA, VIB, VIC, VID, VE1, VE2, DISABLE1, DISABLE2 | -0.5 | V | 18 | |||
| Output Voltages (max = VDDO2 + 0.5 V) | VOA, VOB, VOC, VOD | -0.5 | V | 18 | |||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 18 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 18 | ||
| Common-Mode Transients | -150 | 150 | kV/μs | 18 | |||
| Propagation Delay tPHL, tPLH (5 V operation) | tPHL, tPLH | 4.8 | 7.2 | 13 | ns | 50% input to 50% output | 4 |
| Pulse Width Distortion PWD (5 V operation) | PWD | 0.5 | 3 | ns | /tPLH − tPHL/ | 4 | |
| Channel Matching Codirectional tPSKCD (5 V operation) | tPSKCD | 0.5 | 3 | ns | 4 | ||
| Channel Matching Opposing Direction tPSKOD (5 V operation) | tPSKOD | 0.5 | 3 | ns | 4 | ||
| Logic Low Output Voltage VOL (5 V operation) | VOL | 0 | 0.1 | V | IOx2 = 20 µA, VIx = VIxL4 | 4 | |
| Logic Low Output Voltage VOL (5 V operation) | VOL | 0.2 | 0.4 | V | IOx2 = 4 mA, VIx = VIxL4 | 4 | |
| Quiescent Supply Current IDD1 (Q) (5 V operation, ADuM141D/ADuM141E) | IDD1 (Q) | 1.6 | 2.46 | mA | VI5 = 0 (E0, D0), 1 (E1, D1) | 4 | |
| Quiescent Supply Current IDD2 (Q) (5 V operation, ADuM141D/ADuM141E) | IDD2 (Q) | 1.9 | 2.62 | mA | VI5 = 0 (E0, D0), 1 (E1, D1) | 4 | |
| Quiescent Supply Current IDD1 (Q) (5 V operation, ADuM141D/ADuM141E) | IDD1 (Q) | 10 | 17 | mA | VI5 = 1 (E0, D0), 0 (E1, D1) | 4 | |
| Quiescent Supply Current IDD2 (Q) (5 V operation, ADuM141D/ADuM141E) | IDD2 (Q) | 6 | 10 | mA | VI5 = 1 (E0, D0), 0 (E1, D1) | 4 | |
| Input Current per Channel II (5 V operation) | II | -10 | 0.01 | 10 | µA | 0 V ≤ VIx ≤ VDDx | 4 |
| VE2 Enable Input Pull-Up Current IPU (5 V operation) | IPU | -10 | -3 | µA | VE2 = 0 V | 4 | |
| Tristate Output Current per Channel IOZ (5 V operation) | IOZ | -10 | 0.01 | 10 | µA | 0 V ≤ VOx ≤ VDDx | 4 |
| Propagation Delay tPHL, tPLH (3.3 V operation) | tPHL, tPLH | 4.8 | 6.8 | 14 | ns | 50% input to 50% output | 6 |
| Pulse Width Distortion PWD (3.3 V operation) | PWD | 0.7 | 3 | ns | /tPLH − tPHL/ | 6 | |
| Channel Matching Codirectional tPSKCD (3.3 V operation) | tPSKCD | 0.7 | 3 | ns | 6 | ||
| Channel Matching Opposing Direction tPSKOD (3.3 V operation) | tPSKOD | 0.7 | 3 | ns | 6 | ||
| Logic Low Output Voltage VOL (3.3 V operation) | VOL | 0 | 0.1 | V | IOx2 = 20 µA, VIx = VIxL4 | 6 | |
| Logic Low Output Voltage VOL (3.3 V operation) | VOL | 0.2 | 0.4 | V | IOx2 = 2 mA, VIx = VIxL4 | 6 | |
| Quiescent Supply Current IDD1 (Q) (3.3 V operation, ADuM141D/ADuM141E) | IDD1 (Q) | 1.5 | 2.36 | mA | VI5 = 0 (E0, D0), 1 (E1, D1) | 6 | |
| Quiescent Supply Current IDD2 (Q) (3.3 V operation, ADuM141D/ADuM141E) | IDD2 (Q) | 1.8 | 2.52 | mA | VI5 = 0 (E0, D0), 1 (E1, D1) | 6 | |
| Quiescent Supply Current IDD1 (Q) (3.3 V operation, ADuM141D/ADuM141E) | IDD1 (Q) | 9.8 | 16.7 | mA | VI5 = 1 (E0, D0), 0 (E1, D1) | 6 | |
| Quiescent Supply Current IDD2 (Q) (3.3 V operation, ADuM141D/ADuM141E) | IDD2 (Q) | 5.7 | 9.7 | mA | VI5 = 1 (E0, D0), 0 (E1, D1) | 6 | |
| Propagation Delay tPHL, tPLH (2.5 V operation) | tPHL, tPLH | 5 | 7 | 14 | ns | 50% input to 50% output | 8 |
| Pulse Width Distortion PWD (2.5 V operation) | PWD | 0.7 | 3 | ns | /tPLH − tPHL/ | 8 | |
| Channel Matching Codirectional tPSKCD (2.5 V operation) | tPSKCD | 0.7 | 3 | ns | 8 | ||
| Channel Matching Opposing Direction tPSKOD (2.5 V operation) | tPSKOD | 0.7 | 3 | ns | 8 | ||
| Logic Low Output Voltage VOL (2.5 V operation) | VOL | 0 | 0.1 | V | IOx2 = 20 µA, VIx = VIxL4 | 8 | |
| Logic Low Output Voltage VOL (2.5 V operation) | VOL | 0.2 | 0.4 | V | IOx2 = 2 mA, VIx = VIxL4 | 8 | |
| Quiescent Supply Current IDD1 (Q) (2.5 V operation, ADuM141D/ADuM141E) | IDD1 (Q) | 1.46 | 2.32 | mA | VI5 = 0 (E0, D0), 1 (E1, D1) | 8 | |
| Quiescent Supply Current IDD2 (Q) (2.5 V operation, ADuM141D/ADuM141E) | IDD2 (Q) | 1.75 | 2.47 | mA | VI5 = 0 (E0, D0), 1 (E1, D1) | 8 | |
| Quiescent Supply Current IDD1 (Q) (2.5 V operation, ADuM141D/ADuM141E) | IDD1 (Q) | 9.7 | 16.6 | mA | VI5 = 1 (E0, D0), 0 (E1, D1) | 8 | |
| Quiescent Supply Current IDD2 (Q) (2.5 V operation, ADuM141D/ADuM141E) | IDD2 (Q) | 5.67 | 9.67 | mA | VI5 = 1 (E0, D0), 0 (E1, D1) | 8 | |
| Propagation Delay tPHL, tPLH (1.8 V operation) | tPHL, tPLH | 5.8 | 8.7 | 15 | ns | 50% input to 50% output | 10 |
| Pulse Width Distortion PWD (1.8 V operation) | PWD | 0.7 | 3 | ns | /tPLH − tPHL/ | 10 | |
| Channel Matching Codirectional tPSKCD (1.8 V operation) | tPSKCD | 0.7 | 3 | ns | 10 | ||
| Channel Matching Opposing Direction tPSKOD (1.8 V operation) | tPSKOD | 0.7 | 3 | ns | 10 | ||
| Logic Low Output Voltage VOL (1.8 V operation) | VOL | 0 | 0.1 | V | IOx2 = 20 µA, VIx = VIxL4 | 10 | |
| Logic Low Output Voltage VOL (1.8 V operation) | VOL | 0.2 | 0.4 | V | IOx2 = 2 mA, VIx = VIxL4 | 10 | |
| Quiescent Supply Current IDD1 (Q) (1.8 V operation, ADuM141D/ADuM141E) | IDD1 (Q) | 1.4 | 2.28 | mA | VI5 = 0 (E0, D0), 1 (E1, D1) | 10 | |
| Quiescent Supply Current IDD2 (Q) (1.8 V operation, ADuM141D/ADuM141E) | IDD2 (Q) | 1.73 | 2.45 | mA | VI5 = 0 (E0, D0), 1 (E1, D1) | 10 | |
| Quiescent Supply Current IDD1 (Q) (1.8 V operation, ADuM141D/ADuM141E) | IDD1 (Q) | 9.6 | 16.5 | mA | VI5 = 1 (E0, D0), 0 (E1, D1) | 10 | |
| Quiescent Supply Current IDD2 (Q) (1.8 V operation, ADuM141D/ADuM141E) | IDD2 (Q) | 5.6 | 9.6 | mA | VI5 = 1 (E0, D0), 0 (E1, D1) | 10 | |
| IC Junction to Ambient Thermal Resistance, R-16 SOIC_N Package | θJA | 76 | °C/W | Thermocouple located at center of package underside | 13 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E in the R-16 narrow body [SOIC_N] package is proof tested by applying an insulation test | 14 |
CAD (KiCad official)
- Symbol:
ADUM141E0BRZ - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
adum141e0brz-etched.step/adum141e0brz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum141e0brz.step/adum141e0brz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (31 pp, sha256
d8dc27340f57bada, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).