component
ADUM1411ARWZ-RL
Public Made by Adomby adom
Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADUM1411ARWZ-RL
Analog Devices · Digital Isolators · SOIC-16-300mil
ADUM1411ARWZ-RL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Side 1 supply voltage of the isolator, specified at 2.7 V to 5.5 V. |
| 2 | GND1 | power_in | Side 1 ground reference; pin 2 is internally connected to pin 8, and the datasheet recommends connecting both to GND1. |
| 3 | VIA | input | Logic input A on side 1 of the isolator. |
| 4 | VIB | input | Logic input B on side 1 of the isolator. |
| 5 | VIC | input | Logic input C on side 1 of the isolator. |
| 6 | VOD | output | Logic output D on side 2 of the isolator. |
| 7 | CTRL1 | input | Default output control for channel D: when VDD2 is off and CTRL1 is high or open, VOD goes high; when CTRL1 is low and VDD2 is off, VOD goes low; this pin has no effect while VDD2 is powered. |
| 8 | GND1 | power_in | Side 1 ground reference; pin 8 is internally connected to pin 2, and the datasheet recommends connecting both to GND1. |
| 9 | GND2 | power_in | Side 2 ground reference; pin 9 is internally connected to pin 15, and the datasheet recommends connecting both to GND2. |
| 10 | CTRL2 | input | Default output control for channels A, B and C: when VDD1 is off and CTRL2 is high or open, VOA, VOB and VOC go high; when CTRL2 is low and VDD1 is off, they go low; this pin has no effect while VDD1 is powered. |
| 11 | VID | input | Logic input D on side 2 of the isolator. |
| 12 | VOC | output | Logic output C on side 2 of the isolator. |
| 13 | VOB | output | Logic output B on side 2 of the isolator. |
| 14 | VOA | output | Logic output A on side 2 of the isolator. |
| 15 | GND2 | power_in | Side 2 ground reference; pin 15 is internally connected to pin 9, and the datasheet recommends connecting both to GND2. |
| 16 | VDD2 | power_in | Side 2 supply voltage of the isolator, specified at 2.7 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD1 supply current, quiescent, ADuM1411 total, 4 channels (5 V supply) | IDD1 (Q) | 2.2 | 2.8 | mA | DC to 1 MHz logic signal frequency | 3 | |
| VDD2 supply current, quiescent, ADuM1411 total, 4 channels (5 V supply) | IDD2 (Q) | 1.8 | 2.4 | mA | DC to 1 MHz logic signal frequency | 3 | |
| Input supply current per channel, quiescent (5 V supply) | IDDI (Q) | 0.5 | 0.73 | mA | 3 | ||
| Output supply current per channel, quiescent (5 V supply) | IDDO (Q) | 0.38 | 0.53 | mA | 3 | ||
| Input current (5 V and 3 V supplies) | IIA, IIB, IIC, IID, ICTRL1, ICTRL2, IDISABLE | -10 | 0.01 | 10 | µA | 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2, 0 V ≤ VDISABLE ≤ VDD1 | 3 |
| Logic high input threshold (5 V supply) | VIH | 2 | V | 3 | |||
| Logic low input threshold (5 V supply) | VIL | 0.8 | V | 3 | |||
| Logic low output voltage (5 V supply) | VOAL, VOBL, VOCL, VODL | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 3 | |
| Logic low output voltage (5 V supply) | VOAL, VOBL, VOCL, VODL | 0.04 | 0.1 | V | IOx = 400 µA, VIx = VIxL | 3 | |
| Logic low output voltage (5 V supply) | VOAL, VOBL, VOCL, VODL | 0.2 | 0.4 | V | IOx = 4 mA, VIx = VIxL | 3 | |
| Minimum pulse width (ARWZ, 5 V supply) | PW | 1000 | ns | CL = 15 pF, CMOS signal levels | 4 | ||
| Maximum data rate (ARWZ, 5 V supply) | 1 | Mbps | CL = 15 pF, CMOS signal levels | 4 | |||
| Propagation delay (ARWZ, 5 V supply) | tPHL, tPLH | 20 | 65 | 100 | ns | CL = 15 pF, CMOS signal levels | 4 |
| Pulse width distortion /tPLH - tPHL/ (ARWZ, 5 V supply) | PWD | 40 | ns | CL = 15 pF, CMOS signal levels | 4 | ||
| Propagation delay skew (ARWZ, 5 V supply) | tPSK | 50 | ns | CL = 15 pF, CMOS signal levels | 4 | ||
| Channel-to-channel matching (ARWZ, 5 V supply) | tPSKCD/OD | 50 | ns | CL = 15 pF, CMOS signal levels | 4 | ||
| Output rise/fall time 10% to 90% (5 V and 3 V supplies) | tR/tF | 2.5 | ns | CL = 15 pF, CMOS signal levels | 4 | ||
| Common-mode transient immunity, logic high output (5 V supply) | /CMH/ | 25 | 35 | kV/µs | VIx = VDD1 or VDD2, VCM = 1000 V, transient amplitude = 800 V | 4 | |
| Common-mode transient immunity, logic low output (5 V supply) | /CML/ | 25 | 35 | kV/µs | VIx = 0 V, VCM = 1000 V, transient amplitude = 800 V | 4 | |
| Refresh rate (5 V and 3 V supplies) | fr | 1.2 | Mbps | 4 | |||
| Input enable time (5 V and 3 V supplies) | tENABLE | 2 | µs | VIA, VIB, VIC, VID = 0 V or VDD1 | 4 | ||
| Input disable time (5 V and 3 V supplies) | tDISABLE | 5 | µs | VIA, VIB, VIC, VID = 0 V or VDD1 | 4 | ||
| VDD1 supply current, quiescent, ADuM1411 total, 4 channels (3 V supply) | IDD1 (Q) | 1 | 1.9 | mA | DC to 1 MHz logic signal frequency | 5 | |
| VDD2 supply current, quiescent, ADuM1411 total, 4 channels (3 V supply) | IDD2 (Q) | 0.9 | 1.7 | mA | DC to 1 MHz logic signal frequency | 5 | |
| Input supply current per channel, quiescent (3 V supply) | IDDI (Q) | 0.25 | 0.38 | mA | 5 | ||
| Output supply current per channel, quiescent (3 V supply) | IDDO (Q) | 0.19 | 0.33 | mA | 5 | ||
| Logic high input threshold (3 V supply) | VIH | 1.6 | V | 5 | |||
| Logic low input threshold (3 V supply) | VIL | 0.4 | V | 5 | |||
| Logic low output voltage (3 V supply) | VOAL, VOBL, VOCL, VODL | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 5 | |
| Logic low output voltage (3 V supply) | VOAL, VOBL, VOCL, VODL | 0.04 | 0.1 | V | IOx = 400 µA, VIx = VIxL | 5 | |
| Logic low output voltage (3 V supply) | VOAL, VOBL, VOCL, VODL | 0.2 | 0.4 | V | IOx = 4 mA, VIx = VIxL | 5 | |
| Minimum pulse width (ARWZ, 3 V supply) | PW | 1000 | ns | CL = 15 pF, CMOS signal levels | 6 | ||
| Maximum data rate (ARWZ, 3 V supply) | 1 | Mbps | CL = 15 pF, CMOS signal levels | 6 | |||
| Propagation delay (ARWZ, 3 V supply) | tPHL, tPLH | 20 | 75 | 100 | ns | CL = 15 pF, CMOS signal levels | 6 |
| Pulse width distortion /tPLH - tPHL/ (ARWZ, 3 V supply) | PWD | 40 | ns | CL = 15 pF, CMOS signal levels | 6 | ||
| Propagation delay skew (ARWZ, 3 V supply) | tPSK | 50 | ns | CL = 15 pF, CMOS signal levels | 6 | ||
| Channel-to-channel matching (ARWZ, 3 V supply) | tPSKCD/OD | 50 | ns | CL = 15 pF, CMOS signal levels | 6 | ||
| Common-mode transient immunity, logic high output (3 V supply) | /CMH/ | 25 | 35 | kV/µs | VIx = VDD1 or VDD2, VCM = 1000 V, transient amplitude = 800 V | 6 | |
| Common-mode transient immunity, logic low output (3 V supply) | /CML/ | 25 | 35 | kV/µs | VIx = 0 V, VCM = 1000 V, transient amplitude = 800 V | 6 | |
| Refresh rate (3 V supply) | fr | 1.1 | Mbps | 6 | |||
| Input enable time (3 V supply) | tENABLE | 2 | µs | VIA, VIB, VIC, VID = 0 V or VDD1 | 6 | ||
| Input disable time (3 V supply) | tDISABLE | 5 | µs | VIA, VIB, VIC, VID = 0 V or VDD1 | 6 | ||
| Operating ambient temperature range | TA | -40 | 105 | °C | 11 | ||
| Supply voltage (VDD1, VDD2) | VDD1, VDD2 | 2.7 | 5.5 | V | All voltages referenced to their respective grounds | 11 | |
| Input signal rise and fall time | 1 | ms | 11 | ||||
| Storage temperature range | TST | -65 | 150 | °C | 12 | ||
| Operating ambient temperature range | TA | -40 | 105 | °C | 12 | ||
| Supply voltage | VDD1, VDD2 | -0.5 | 7 | V | 12 | ||
| Input voltage | VIA, VIB, VIC, VID, VCTRL1, VCTRL2, VDISABLE | -0.5 | V | 12 | |||
| Output voltage | VOA, VOB, VOC, VOD | -0.5 | V | 12 | |||
| Average output current per pin, side 1 | IO1 | -18 | 18 | mA | 12 | ||
| Average output current per pin, side 2 | IO2 | -22 | 22 | mA | 12 | ||
| Common-mode transients across isolation barrier | -100 | 100 | kV/µs | 12 | |||
| Logic high output voltage (5 V supply) | VOAH, VOBH | 5 | V | IOx = -20 µA, VIx = VIxH | 3 | ||
| Logic high output voltage (5 V supply) | VOCH, VODH | 4.8 | V | IOx = -4 mA, VIx = VIxH | 3 | ||
| Logic high output voltage (3 V supply) | VOAH, VOBH | 3 | V | IOx = -20 µA, VIx = VIxH | 5 | ||
| Logic high output voltage (3 V supply) | VOCH, VODH | 2.8 | V | IOx = -4 mA, VIx = VIxH | 5 | ||
| Thermal resistance, junction to case, side 1 | θJCI | 33 | °C/W | Thermocouple located at bottom center of package | 10 | ||
| Thermal resistance, junction to case, side 2 | θJCO | 28 | °C/W | Thermocouple located at bottom center of package | 10 |
CAD (KiCad official)
- Symbol:
ADUM1411ARWZ-RL - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
adum1411arwz-rl-etched.step/adum1411arwz-rl-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum1411arwz-rl.step/adum1411arwz-rl.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
a7d65f55641aef4b, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).