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ADUM1410BRWZ-RL

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Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADUM1410BRWZ-RL

Analog Devices · Digital Isolators · SOIC-16-300mil

ADUM1410BRWZ-RL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, 2.7 V to 5.5 V.
2 GND1 power_in Ground reference for isolator side 1; internally connected to pin 8, and connecting both to GND1 is recommended.
3 VIA input Logic input A.
4 VIB input Logic input B.
5 VIC input Logic input C.
6 VID input Logic input D.
7 DISABLE input Input disable; disables the isolator inputs and halts the dc refresh circuits, with outputs taking the logic state determined by CTRL2.
8 GND1 power_in Ground reference for isolator side 1; internally connected to pin 2, and connecting both to GND1 is recommended.
9 GND2 power_in Ground reference for isolator side 2; internally connected to pin 15, and connecting both to GND2 is recommended.
10 CTRL2 input Default output control; VOA-VOD are high when CTRL2 is high or disconnected and VDD1 is off, low when CTRL2 is low and VDD1 is off, and has no effect while VDD1 is powered.
11 VOD output Logic output D.
12 VOC output Logic output C.
13 VOB output Logic output B.
14 VOA output Logic output A.
15 GND2 power_in Ground reference for isolator side 2; internally connected to pin 9, and connecting both to GND2 is recommended.
16 VDD2 power_in Supply voltage for isolator side 2, 2.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltages (VDD1, VDD2) recommended VDD1, VDD2 2.7 5.5 V All voltages relative to their respective ground 11
Operating Temperature TA -40 105 °C 11
Input Signal Rise and Fall Times 1 ms 11
Supply Voltages (VDD1, VDD2) VDD1, VDD2 -0.5 7 V Relative to their respective ground 12
Storage Temperature TST -65 150 °C 12
Ambient Operating Temperature TA -40 105 °C 12
Average Output Current per Pin, Side 1 IO1 -18 18 mA 12
Average Output Current per Pin, Side 2 IO2 -22 22 mA 12
Common-Mode Transients -100 100 kV/μs Refers to common-mode transients across the insulation barrier 12
VDD1 Supply Current, Quiescent (ADuM1410, four channels) IDD1 (Q) 2.4 3.2 mA DC to 1 MHz logic signal frequency 3
VDD2 Supply Current, Quiescent (ADuM1410, four channels) IDD2 (Q) 1.2 1.6 mA DC to 1 MHz logic signal frequency 3
VDD1 Supply Current, 10 Mbps (ADuM1410 BRWZ) IDD1 (10) 8.8 12 mA 5 MHz logic signal frequency 3
VDD2 Supply Current, 10 Mbps (ADuM1410 BRWZ) IDD2 (10) 2.8 4 mA 5 MHz logic signal frequency 3
Input Supply Current per Channel, Quiescent IDDI (Q) 0.5 0.73 mA 3
Output Supply Current per Channel, Quiescent IDDO (Q) 0.38 0.53 mA 3
Input Currents IIA, IIB, IIC, IID, ICTRL1, ICTRL2, IDISABLE -10 0.01 10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2; 0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2; 0 V ≤ VDISABLE ≤ VDD1 3
Logic High Input Threshold VIH 2 V 3
Logic Low Input Threshold VIL 0.8 V 3
Logic Low Output Voltage (20 µA load) VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 µA, VIx = VIxL 3
Logic Low Output Voltage (400 µA load) VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 3
Logic Low Output Voltage (4 mA load) VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 3
Minimum Pulse Width (BRWZ) PW 100 ns CL = 15 pF, CMOS signal levels 4
Maximum Data Rate (BRWZ) 10 Mbps CL = 15 pF, CMOS signal levels 4
Propagation Delay (BRWZ, 5 V) tPHL, tPLH 20 30 50 ns CL = 15 pF, CMOS signal levels 4
Pulse Width Distortion (BRWZ) PWD 5 ns /tPLH − tPHL/, CL = 15 pF, CMOS signal levels 4
Change vs. Temperature (BRWZ) 5 ps/°C CL = 15 pF, CMOS signal levels 4
Propagation Delay Skew (BRWZ) tPSK 30 ns CL = 15 pF, CMOS signal levels 4
Channel-to-Channel Matching, Codirectional Channels (BRWZ) tPSKCD 5 ns CL = 15 pF, CMOS signal levels 4
Channel-to-Channel Matching, Opposing-Directional Channels (BRWZ) tPSKOD 6 ns CL = 15 pF, CMOS signal levels 4
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels 4
Common-Mode Transient Immunity at Logic High Output /CMH/ 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 4
Common-Mode Transient Immunity at Logic Low Output /CML/ 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 4
Input Enable Time tENABLE 2 µs VIA, VIB, VIC, VID = 0 V or VDD1 4
Input Disable Time tDISABLE 5 µs VIA, VIB, VIC, VID = 0 V or VDD1 4
Capacitance (Input-to-Output) CI-O 2.2 pF f = 1 MHz 10
Input Capacitance CI 4 pF Input capacitance from any input data pin to ground 10
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located at center of package underside 10
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W Thermocouple located at center of package underside 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-10, each ADuM141x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) mark 10

CAD (KiCad official)

  • Symbol: ADUM1410BRWZ-RL
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: adum1410brwz-rl-etched.step / adum1410brwz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1410brwz-rl.step / adum1410brwz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 f92ec69a5d025b46, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF