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ADUM1410ARWZ-RL

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Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADUM1410ARWZ-RL

Analog Devices · Digital Isolators · SOIC-16-300mil

ADUM1410ARWZ-RL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, 2.7 V to 5.5 V.
2 GND1 power_in Ground 1, the ground reference for isolator side 1; pin 2 is internally connected to pin 8, and connecting both to GND1 is recommended.
3 VIA input Logic input A; logic high threshold VIH is 2.0 V minimum and logic low threshold VIL is 0.8 V maximum.
4 VIB input Logic input B; logic high threshold VIH is 2.0 V minimum and logic low threshold VIL is 0.8 V maximum.
5 VIC input Logic input C; logic high threshold VIH is 2.0 V minimum and logic low threshold VIL is 0.8 V maximum.
6 VID input Logic input D; logic high threshold VIH is 2.0 V minimum and logic low threshold VIL is 0.8 V maximum.
7 DISABLE input Input disable; disables the isolator inputs and halts the dc refresh circuits, so outputs take the default state set by CTRL2.
8 GND1 power_in Ground 1, the ground reference for isolator side 1; pin 8 is internally connected to pin 2, and connecting both to GND1 is recommended.
9 GND2 power_in Ground 2, the ground reference for isolator side 2; pin 9 is internally connected to pin 15, and connecting both to GND2 is recommended.
10 CTRL2 input Default output control; outputs VOA to VOD go high when CTRL2 is high or disconnected and VDD1 is off, go low when CTRL2 is low and VDD1 is off, and CTRL2 has no effect while VDD1 is powered.
11 VOD output Logic output D.
12 VOC output Logic output C.
13 VOB output Logic output B.
14 VOA output Logic output A.
15 GND2 power_in Ground 2, the ground reference for isolator side 2; pin 15 is internally connected to pin 9, and connecting both to GND2 is recommended.
16 VDD2 power_in Supply voltage for isolator side 2, 2.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Supply Current per Channel, Quiescent (5 V operation) IDDI (Q) 0.5 0.73 mA 3
Output Supply Current per Channel, Quiescent (5 V operation) IDDO (Q) 0.38 0.53 mA 3
ADuM1410 VDD1 Supply Current, DC to 2 Mbps (5 V operation) IDD1 (Q) 2.4 3.2 mA DC to 1 MHz logic signal frequency 3
ADuM1410 VDD2 Supply Current, DC to 2 Mbps (5 V operation) IDD2 (Q) 1.2 1.6 mA DC to 1 MHz logic signal frequency 3
Logic High Input Threshold (5 V operation) VIH 2 V 3
Logic Low Input Threshold (5 V operation) VIL 0.8 V 3
Logic Low Output Voltage, 20 μA load (5 V operation) VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 μA, VIx = VIxL 3
Logic Low Output Voltage, 400 μA load (5 V operation) VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 3
Logic Low Output Voltage, 4 mA load (5 V operation) VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 3
Logic High Output Voltage VOAH, VOBH, 20 μA (5 V operation); min printed as (VDD1 or VDD2) − 0.1 V VOAH, VOBH 5 V IOx = −20 μA, VIx = VIxH 3
Logic High Output Voltage VOCH, VODH, 4 mA (5 V operation); min printed as (VDD1 or VDD2) − 0.4 V VOCH, VODH 4.8 V IOx = −4 mA, VIx = VIxH 3
Minimum Pulse Width (5 V operation, ARWZ) PW 1000 ns CL = 15 pF, CMOS signal levels 3
Maximum Data Rate (5 V operation, ARWZ) 1 Mbps CL = 15 pF, CMOS signal levels 3
Propagation Delay (5 V operation, ARWZ) tPHL, tPLH 20 65 100 ns CL = 15 pF, CMOS signal levels 3
Pulse Width Distortion (5 V operation, ARWZ) /tPLH − tPHL/ 40 ns CL = 15 pF, CMOS signal levels 3
Propagation Delay Skew (5 V operation, ARWZ) tPSK 50 ns CL = 15 pF, CMOS signal levels 4
Channel-to-Channel Matching (5 V operation, ARWZ) tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels 4
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels 4
Common-Mode Transient Immunity at Logic High Output (5 V operation) /CMH/ 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 4
Common-Mode Transient Immunity at Logic Low Output (5 V operation) /CML/ 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 4
Input Enable Time (5 V operation) tENABLE 2 μs VIA, VIB, VIC, VID = 0 V or VDD1 4
Input Disable Time (5 V operation) tDISABLE 5 μs VIA, VIB, VIC, VID = 0 V or VDD1 4
Input Supply Current per Channel, Quiescent (3 V operation) IDDI (Q) 0.25 0.38 mA 5
Output Supply Current per Channel, Quiescent (3 V operation) IDDO (Q) 0.19 0.33 mA 5
ADuM1410 VDD1 Supply Current, DC to 2 Mbps (3 V operation) IDD1 (Q) 1.2 1.6 mA DC to 1 MHz logic signal frequency 5
ADuM1410 VDD2 Supply Current, DC to 2 Mbps (3 V operation) IDD2 (Q) 0.8 1 mA DC to 1 MHz logic signal frequency 5
Input Currents (3 V operation) IIA, IIB, IIC, IID, ICTRL1, ICTRL2, IDISABLE -10 0.01 10 μA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2, 0 V ≤ VDISABLE ≤ VDD1 5
Logic High Input Threshold (3 V operation) VIH 1.6 V 5
Logic Low Input Threshold (3 V operation) VIL 0.4 V 5
Logic Low Output Voltage, 20 μA load (3 V operation) VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 μA, VIx = VIxL 5
Logic Low Output Voltage, 400 μA load (3 V operation) VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 μA, VIx = VIxL 5
Logic Low Output Voltage, 4 mA load (3 V operation) VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 5
Logic High Output Voltage VOAH, VOBH, 20 μA (3 V operation); min printed as (VDD1 or VDD2) − 0.1 V VOAH, VOBH 3 V IOx = −20 μA, VIx = VIxH 5
Logic High Output Voltage VOCH, VODH, 4 mA (3 V operation); min printed as (VDD1 or VDD2) − 0.4 V VOCH, VODH 2.8 V IOx = −4 mA, VIx = VIxH 5
Minimum Pulse Width (3 V operation, ARWZ) PW 1000 ns CL = 15 pF, CMOS signal levels 5
Maximum Data Rate (3 V operation, ARWZ) 1 Mbps CL = 15 pF, CMOS signal levels 5
Propagation Delay (3 V operation, ARWZ) tPHL, tPLH 20 75 100 ns CL = 15 pF, CMOS signal levels 5
Pulse Width Distortion (3 V operation, ARWZ) /tPLH − tPHL/ 40 ns CL = 15 pF, CMOS signal levels 5
Propagation Delay Skew (3 V operation, ARWZ) tPSK 50 ns CL = 15 pF, CMOS signal levels 5
Channel-to-Channel Matching (3 V operation, ARWZ) tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels 6
Output Rise/Fall Time (10% to 90%, 3 V operation) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels 6
Common-Mode Transient Immunity at Logic High Output (3 V operation) /CMH/ 25 35 kV/μs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 6
Common-Mode Transient Immunity at Logic Low Output (3 V operation) /CML/ 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 6
Input Enable Time (3 V operation) tENABLE 2 μs VIA, VIB, VIC, VID = 0 V or VDD1 6
Input Disable Time (3 V operation) tDISABLE 5 μs VIA, VIB, VIC, VID = 0 V or VDD1 6
Operating Temperature TA -40 105 °C 11
Supply Voltages VDD1, VDD2 2.7 5.5 V Relative to their respective ground 11
Input Signal Rise and Fall Times 1 ms 11
Storage Temperature TST -65 150 °C 12
Ambient Operating Temperature TA -40 105 °C 12
Supply Voltages VDD1, VDD2 -0.5 7 V Relative to their respective ground 12
Input Voltages; max printed as VDDI + 0.5 V VIA, VIB, VIC, VID, VCTRL1, VCTRL2, VDISABLE -0.5 V 12
Output Voltages; max printed as VDDO + 0.5 V VOA, VOB, VOC, VOD -0.5 V 12
Average Output Current per Pin, Side 1 IO1 -18 18 mA 12
Average Output Current per Pin, Side 2 IO2 -22 22 mA 12
Common-Mode Transients -100 100 kV/μs 12
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located at center of package underside 10
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W Thermocouple located at center of package underside 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-10, each ADuM141x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) mark 10

CAD (KiCad official)

  • Symbol: ADUM1410ARWZ-RL
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: adum1410arwz-rl-etched.step / adum1410arwz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1410arwz-rl.step / adum1410arwz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 8040a430e94067ef, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF