ADUM140E1BRZ from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Supply voltage for isolator side 1.
2	GND1	power_in	Ground reference for isolator side 1.
3	VIA	input	Logic input A.
4	VIB	input	Logic input B.
5	VIC	input	Logic input C.
6	VID	input	Logic input D.
7	NIC	unconnected	No internal connection; leave this pin floating.
8	GND1	power_in	Ground reference for isolator side 1.
9	GND2	power_in	Ground reference for isolator side 2.
10	VE2	input	Active-high output enable 2; outputs VOA, VOB, VOC and VOD are enabled when high or disconnected and go to high-Z when low.
11	VOD	tri_state	Logic output D, high-Z when VE2 is low.
12	VOC	tri_state	Logic output C, high-Z when VE2 is low.
13	VOB	tri_state	Logic output B, high-Z when VE2 is low.
14	VOA	tri_state	Logic output A, high-Z when VE2 is low.
15	GND2	power_in	Ground reference for isolator side 2.
16	VDD2	power_in	Supply voltage for isolator side 2.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-16
Category	Communication Interface Chip/UART/485/232
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Propagation Delay (5 V)	tPHL, tPLH		7.2	13	ns	50% input to 50% output; 4.5 V ≤ VDDx ≤ 5.5 V (min 4.8 printed)	4
Pulse Width Distortion (5 V)	PWD		0.5	3	ns	/tPLH − tPHL/	4
Propagation Delay Skew (5 V)	tPSK			6.1	ns	Between any two units at the same temperature, voltage, and load	4
Channel Matching Codirectional (5 V)	tPSKCD		0.5	3	ns		4
Channel Matching Opposing Direction (5 V)	tPSKOD		0.5	3	ns		4
Pulse Width (5 V)	PW	6.6			ns	Within pulse width distortion (PWD) limit	4
Data Rate (5 V)		150			Mbps	Within PWD limit	4
Output Voltage Logic Low (5 V)	VOL		0	0.1	V	IOx = 20 µA, VIx = VIxL	4
Output Voltage Logic Low (5 V)	VOL		0.2	0.4	V	IOx = 4 mA, VIx = VIxL	4
Input Current per Channel	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx	4
VE2 Enable Input Pull-Up Current	IPU	-10		-3	µA	VE2 = 0 V	4
Tristate Output Current per Channel	IOZ	-10	0.01	10	µA	0 V ≤ VOx ≤ VDDx	4
Quiescent Supply Current Side 1 (5 V)	IDD1 (Q)		1.2	2.2	mA	ADuM140E; VI = 1 (E1)	4
Quiescent Supply Current Side 2 (5 V)	IDD2 (Q)		2	2.72	mA	ADuM140E; VI = 1 (E1)	4
Quiescent Supply Current Side 1 (5 V)	IDD1 (Q)		12	20	mA	ADuM140E; VI = 0 (E1)	4
Quiescent Supply Current Side 2 (5 V)	IDD2 (Q)		2	2.92	mA	ADuM140E; VI = 0 (E1)	4
Common-Mode Transient Immunity High	/CMH/	75	100		kV/µs	VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V	5
Common-Mode Transient Immunity Low	/CML/	75	100		kV/µs	VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V	5
Propagation Delay (3.3 V)	tPHL, tPLH		6.8	14	ns	50% input to 50% output; 3.0 V ≤ VDDx ≤ 3.6 V (min 4.8 printed)	6
Pulse Width Distortion (3.3 V)	PWD		0.7	3	ns	/tPLH − tPHL/	6
Propagation Delay Skew (3.3 V)	tPSK			7.5	ns	Between any two units at the same temperature, voltage, and load	6
Propagation Delay (2.5 V)	tPHL, tPLH		7	14	ns	50% input to 50% output; 2.25 V ≤ VDDx ≤ 2.75 V (min 5.0 printed)	8
Pulse Width Distortion (2.5 V)	PWD		0.7	3	ns	/tPLH − tPHL/	8
Propagation Delay Skew (2.5 V)	tPSK			6.8	ns	Between any two units at the same temperature, voltage, and load	8
Propagation Delay (1.8 V)	tPHL, tPLH		8.7	15	ns	50% input to 50% output; 1.7 V ≤ VDDx ≤ 1.9 V (min 5.8 printed)	10
Pulse Width Distortion (1.8 V)	PWD		0.7	3	ns	/tPLH − tPHL/	10
Propagation Delay Skew (1.8 V)	tPSK			7	ns	Between any two units at the same temperature, voltage, and load	10
Propagation Delay Minimum (5 V)	tPHL, tPLH	4.8			ns	50% input to 50% output	4
Output Rise/Fall Time (5 V)	tR/tF		2.5		ns	10% to 90%	5
PWD Change vs. Temperature (5 V)			1.5		ps/°C		4
Jitter (5 V)			490		ps p-p	See the Jitter Measurement section	4
UVLO Positive VDDx Threshold	VDDxUV+		1.6		V		5
UVLO Negative VDDx Threshold	VDDxUV−		1.5		V		5
Operating Temperature	TA	-40		125	°C		17
Supply Voltages	VDD1, VDD2	1.7		5.5	V		17
Input Signal Rise and Fall Times				1	ms		17
Storage Temperature Range	TST	-65		150	°C	TA = 25°C	18
Ambient Operating Temperature Range	TA	-40		125	°C		18
Maximum Fault Junction Temperature per DIN V VDE V 0884-11	TJ			150	°C		18
Maximum Fault Junction Temperature per Mold Compound	TJ			300	°C		18
Supply Voltages	VDD1, VDD2	-0.5		7	V		18
Input Voltages	VIA, VIB, VIC, VID, VE1, VE2, DISABLE1, DISABLE2	-0.5			V	Max is VDDI1 + 0.5 V	18
Output Voltages	VOA, VOB, VOC, VOD	-0.5			V	Max is VDDO2 + 0.5 V	18
Side 1 Output Current	IO1	-10		10	mA	Average output current per pin	18
Side 2 Output Current	IO2	-10		10	mA	Average output current per pin	18
Common-Mode Transients		-150		150	kV/µs	Across the insulation barrier	18
IC Junction to Ambient Thermal Resistance, R-16 SOIC_N	θJA		76		°C/W	Thermocouple located at center of package underside	13
Rated Dielectric Insulation Voltage, R-16 SOIC_N			3000		V rms	1-minute duration	12
Capacitance (Input to Output)	CI-O		2.2		pF	f = 1 MHz	13
Input Capacitance	CI		4		pF	From any input data pin to ground	13

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pC		In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E in the R-16 narrow body [SOIC_N] package is proof tested by applying an insulation test	14

CAD (KiCad official)

Symbol: ADUM140E1BRZ
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: adum140e1brz-etched.step / adum140e1brz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum140e1brz.step / adum140e1brz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (31 pp, sha256 d8dc27340f57bada, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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ADUM140E1BRZ

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