main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers adum140d0brwz-rl: viewers · Ray 8d ago
adum140d0brwz-rl-etched.glb Publish 0.1.0 · Ray 8d ago
adum140d0brwz-rl-etched.step adum140d0brwz-rl: factory component page (tier=lcsc) · Ray 8d ago
adum140d0brwz-rl-hero.glb adum140d0brwz-rl: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
adum140d0brwz-rl-hero.overlay.json Publish 0.1.0 · Ray 8d ago
adum140d0brwz-rl.glb Publish 0.1.0 · Ray 8d ago
adum140d0brwz-rl.kicad_mod Publish 0.1.0 · Ray 8d ago
adum140d0brwz-rl.kicad_sym Publish 0.1.0 · Ray 8d ago
adum140d0brwz-rl.lbr Publish 0.1.0 · Ray 8d ago
adum140d0brwz-rl.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago

ADUM140D0BRWZ-RL

Analog Devices · Digital Isolators · SOIC-16-300mil

ADUM140D0BRWZ-RL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Isolator side 1 supply voltage, which must be within the recommended 1.7 V to 5.5 V range (VDD1 and VDD2).
2 GND1 power_in Side 1 reference ground for the isolator.
3 VIA input Logic input A on side 1.
4 VIB input Logic input B on side 1.
5 VIC input Logic input C on side 1.
6 VID input Logic input D on side 1.
7 DISABLE1 input Input disable for side 1; when active it disables the isolator inputs and the output goes to the fail-safe state set by the ordering option (high for the D1 variant, low for the D0 variant).
8 GND1 power_in Side 1 reference ground for the isolator.
9 GND2 power_in Side 2 reference ground for the isolator.
10 NIC unconnected No internal connection; this pin must be left floating.
11 VOD output Logic output D on side 2.
12 VOC output Logic output C on side 2.
13 VOB output Logic output B on side 2.
14 VOA output Logic output A on side 2.
15 GND2 power_in Side 2 reference ground for the isolator.
16 VDD2 power_in Isolator side 2 supply voltage, which must be within the recommended 1.7 V to 5.5 V range (VDD1 and VDD2).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Pulse width PW 6.6 ns 在脉宽失真(PWD)限值内 3
Pulse width distortion PWD 0.5 3 ns /tPLH − tPHL/ 3
Propagation delay tPHL,tPLH 4.8 7.2 13 ns 50%输入至50%输出 3
Propagation delay skew tPSK 6.1 ns 相同温度、电压和负载下的任意两个单元之间 3
Channel matching, codirectional tPSKCD 0.5 3 ns 同向 3
Channel matching, opposing directional tPSKOD 0.5 3 ns 反向 3
Jitter, peak-to-peak 490 ps p-p 参见“抖动测量”部分 3
Jitter, rms 70 ps rms 参见“抖动测量”部分 3
Propagation delay temperature drift 1.5 ps/°C 3
Logic high input threshold VIH 0.7 ×VDDx 3
Logic low input threshold VIL 0.3 ×VDDx 3
Logic low output voltage VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 3
Logic low output voltage VOL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 3
Per-channel input current II -10 0.01 10 µA 0 V ≤ VIx ≤ VDDx 3
Three-state output leakage current per channel IOZ -10 0.01 10 µA 0 V ≤ VOx ≤ VDDx 3
DISABLE1 input pull-down current IPD 9 15 µA DISABLE1 = VDDx 3
Dynamic input supply current IDDI (D) 0.01 mA/Mbps 输入切换,50%占空比 3
Dynamic output supply current IDDO (D) 0.02 mA/Mbps 输入切换,50%占空比 3
UVLO positive VDDx threshold VDDxUV+ 1.6 V 4
UVLO negative VDDx threshold VDDxUV− 1.5 V 4
UVLO VDDx hysteresis VDDxUVH 0.1 V 4
Output rise/fall time tR/tF 2.5 ns 10%至90% 4
Common-mode transient immunity, high /CMH/ 75 100 kV/µs VIx = VDDx,VCM = 1000 V,瞬变幅度 = 800 V 4
Common-mode transient immunity, low /CML/ 75 100 kV/µs VIx = 0 V,VCM = 1000 V,瞬变幅度 = 800 V 4
Side 1 quiescent supply current IDD1 (Q) 1.2 2.2 mA VI = 0 (E0,D0),1 (E1,D1) 3
Side 2 quiescent supply current IDD2 (Q) 2 2.72 mA VI = 0 (E0,D0),1 (E1,D1) 3
Side 1 quiescent supply current IDD1 (Q) 12 20 mA VI = 1 (E0,D0),0 (E1,D1) 3
Side 2 quiescent supply current IDD2 (Q) 2 2.92 mA VI = 1 (E0,D0),0 (E1,D1) 3

CAD (KiCad official)

  • Symbol: ADUM140D0BRWZ-RL
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: adum140d0brwz-rl-etched.step / adum140d0brwz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum140d0brwz-rl.step / adum140d0brwz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (27 pp, sha256 190352b604fe3edd, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF