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ADUM1402CRWZ-RL

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Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADUM1402CRWZ-RL

Analog Devices · Digital Isolators · SOIC-16-300mil

ADUM1402CRWZ-RL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, specified at 2.7 V to 5.5 V relative to GND1 in the recommended operating conditions.
2 GND1 power_in Ground 1, the ground reference for isolator side 1; internally connected to pin 8, and connecting both to GND1 is recommended.
3 VIA input Logic input A on side 1 of the isolation barrier.
4 VIB input Logic input B on side 1 of the isolation barrier.
5 VOC output Logic output C on side 2, enabled and disabled by the VE1 input.
6 VOD output Logic output D on side 2, enabled and disabled by the VE1 input.
7 VE1 input Active-high output enable 1: VOC and VOD are enabled when high or disconnected and disabled when low; connecting it to an external logic high or low is recommended in noisy environments.
8 GND1 power_in Ground 1, the ground reference for isolator side 1; internally connected to pin 2, and connecting both to GND1 is recommended.
9 GND2 power_in Ground 2, the ground reference for isolator side 2; internally connected to pin 15, and connecting both to GND2 is recommended.
10 VE2 input Active-high output enable 2: VOA and VOB are enabled when high or disconnected and disabled when low; connecting it to an external logic high or low is recommended in noisy environments.
11 VID input Logic input D on side 2 of the isolation barrier.
12 VIC input Logic input C on side 2 of the isolation barrier.
13 VOB output Logic output B on side 2, enabled and disabled by the VE2 input.
14 VOA output Logic output A on side 2, enabled and disabled by the VE2 input.
15 GND2 power_in Ground 2, the ground reference for isolator side 2; internally connected to pin 9, and connecting both to GND2 is recommended.
16 VDD2 power_in Supply voltage for isolator side 2, specified at 2.7 V to 5.5 V relative to GND2 in the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Logic High Input Threshold VIH, VEH 2 V 5 V operation 4
Logic Low Input Threshold VIL, VEL 0.8 V 5 V operation 4
Input Currents IIA, IIB, IIC, IID, IE1, IE2 -10 0.01 10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 4
Input Supply Current per Channel, Quiescent IDDI (Q) 0.5 0.53 mA 4
Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.21 mA 4
ADuM1402 VDD1 or VDD2 Supply Current, DC to 2 Mbps IDD1 (Q), IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq. 4
ADuM1402 VDD1 or VDD2 Supply Current, 10 Mbps IDD1 (10), IDD2 (10) 5.6 7 mA 5 MHz logic signal freq. 4
ADuM1402 VDD1 or VDD2 Supply Current, 90 Mbps IDD1 (90), IDD2 (90) 44 62 mA 45 MHz logic signal freq. 4
Logic Low Output Voltage VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 µA, VIx = VIxL 4
Logic Low Output Voltage VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 4
Logic Low Output Voltage VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 3.2 mA, VIx = VIxL 4
Logic High Output Voltage VOAH, VOBH, VOCH, VODH 5 V IOx = −20 µA, VIx = VIxH; minimum printed as (VDD1 or VDD2) − 0.1 4
Logic High Output Voltage VOAH, VOBH, VOCH, VODH 4.8 V IOx = −3.2 mA, VIx = VIxH; minimum printed as (VDD1 or VDD2) − 0.4 4
Minimum Pulse Width (CRW grade) PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels 5
Maximum Data Rate (CRW grade) 90 120 Mbps CL = 15 pF, CMOS signal levels 5
Propagation Delay (CRW grade) tPHL, tPLH 18 27 32 ns CL = 15 pF, CMOS signal levels 5
Pulse Width Distortion (CRW grade) /tPLH − tPHL/ 0.5 2 ns CL = 15 pF, CMOS signal levels 5
Propagation Delay Skew (CRW grade) tPSK 10 ns CL = 15 pF, CMOS signal levels 5
Channel-to-Channel Matching, Codirectional (CRW grade) tPSKCD 2 ns CL = 15 pF, CMOS signal levels 5
Channel-to-Channel Matching, Opposing-Directional (CRW grade) tPSKOD 5 ns CL = 15 pF, CMOS signal levels 5
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels 5
Output Disable Propagation Delay (High/Low to High Impedance) tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels 5
Output Enable Propagation Delay (High Impedance to High/Low) tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels 5
Common-Mode Transient Immunity at Logic High Output /CMH/ 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 5
Common-Mode Transient Immunity at Logic Low Output /CML/ 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 5
Refresh Rate fr 1.2 Mbps 5
Input Dynamic Supply Current per Channel IDDI (D) 0.19 mA/Mbps 5
Output Dynamic Supply Current per Channel IDDO (D) 0.05 mA/Mbps 5
Operating Temperature (TA), grade 1 TA -40 105 °C Does not apply to W automotive grade 20
Supply Voltages (VDD1, VDD2), grade 1 VDD1, VDD2 2.7 5.5 V All voltages relative to their respective ground 20
Input Signal Rise and Fall Times 1 ms 20
Storage Temperature TST -65 150 °C 21
Ambient Operating Temperature, grade 1 TA -40 105 °C Does not apply to W automotive grade 21
Supply Voltages VDD1, VDD2 -0.5 7 V All voltages relative to their respective ground 21
Input Voltage VIA, VIB, VIC, VID, VE1, VE2 -0.5 V Upper limit printed as VDDI + 0.5 V 21
Output Voltage VOA, VOB, VOC, VOD -0.5 V Upper limit printed as VDDO + 0.5 V 21
Average Output Current per Pin, Side 1 IO1 -18 18 mA 21
Average Output Current per Pin, Side 2 IO2 -22 22 mA 21
Common-Mode Transients -100 100 kV/µs Across the insulation barrier 21
IC Junction to Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located at center of package underside 19
IC Junction to Case Thermal Resistance, Side 2 θJCO 28 °C/W Thermocouple located at center of package underside 19

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC 2 In accordance with DIN V VDE V 0884-10, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The 19

CAD (KiCad official)

  • Symbol: ADUM1402CRWZ-RL
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: adum1402crwz-rl-etched.step / adum1402crwz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1402crwz-rl.step / adum1402crwz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (31 pp, sha256 416fb6e11b4027f6, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF