component
ADUM1402BRWZ-RL
Public Made by Adomby adom
Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownADUM1402BRWZ-RL
Analog Devices · Digital Isolators · SOIC-16-300mil
ADUM1402BRWZ-RL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified at 2.7 V to 5.5 V relative to GND1 under the recommended operating conditions. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1; internally connected to pin 8, and connecting both to GND1 is recommended. |
| 3 | VIA | input | Logic input A on the side 1 encoder for channel A. |
| 4 | VIB | input | Logic input B on the side 1 encoder for channel B. |
| 5 | VOC | output | Logic output C on the side 1 decoder, enabled and disabled by VE1; disabled to high impedance when VE1 is low. |
| 6 | VOD | output | Logic output D on the side 1 decoder, enabled and disabled by VE1; disabled to high impedance when VE1 is low. |
| 7 | VE1 | input | Output enable 1, active-high logic input for VOC and VOD; outputs are enabled when high or disconnected and disabled when low, and connecting to an external logic level is recommended in noisy environments. |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1; internally connected to pin 2, and connecting both to GND1 is recommended. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2; internally connected to pin 15, and connecting both to GND2 is recommended. |
| 10 | VE2 | input | Output enable 2, active-high logic input for VOA and VOB; outputs are enabled when high or disconnected and disabled when low, and connecting to an external logic level is recommended in noisy environments. |
| 11 | VID | input | Logic input D on the side 2 encoder for channel D. |
| 12 | VIC | input | Logic input C on the side 2 encoder for channel C. |
| 13 | VOB | output | Logic output B on the side 2 decoder, enabled and disabled by VE2; disabled to high impedance when VE2 is low. |
| 14 | VOA | output | Logic output A on the side 2 decoder, enabled and disabled by VE2; disabled to high impedance when VE2 is low. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2; internally connected to pin 9, and connecting both to GND2 is recommended. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, specified at 2.7 V to 5.5 V relative to GND2 under the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Current per Channel, Quiescent | IDDI (Q) | 0.5 | 0.53 | mA | 4 | ||
| Output Supply Current per Channel, Quiescent | IDDO (Q) | 0.19 | 0.21 | mA | 4 | ||
| ADuM1402 VDD1 or VDD2 Supply Current, DC to 2 Mbps | IDD1 (Q), IDD2 (Q) | 1.5 | 2.1 | mA | DC to 1 MHz logic signal freq. | 4 | |
| ADuM1402 VDD1 or VDD2 Supply Current, 10 Mbps (BRW and CRW) | IDD1 (10), IDD2 (10) | 5.6 | 7 | mA | 5 MHz logic signal freq. | 4 | |
| Input Currents | IIA, IIB, IIC, IID, IE1, IE2 | -10 | 0.01 | 10 | µA | 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 | 4 |
| Logic High Input Threshold | VIH, VEH | 2 | V | 4 | |||
| Logic Low Input Threshold | VIL, VEL | 0.8 | V | 4 | |||
| Logic Low Output Voltages | VOAL, VOBL, VOCL, VODL | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 4 | |
| Logic Low Output Voltages | VOAL, VOBL, VOCL, VODL | 0.04 | 0.1 | V | IOx = 400 µA, VIx = VIxL | 4 | |
| Logic Low Output Voltages | VOAL, VOBL, VOCL, VODL | 0.2 | 0.4 | V | IOx = 3.2 mA, VIx = VIxL | 4 | |
| Minimum Pulse Width (BRW) | PW | 100 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Maximum Data Rate (BRW) | 10 | Mbps | CL = 15 pF, CMOS signal levels | 5 | |||
| Propagation Delay (BRW) | tPHL, tPLH | 20 | 32 | 50 | ns | CL = 15 pF, CMOS signal levels | 5 |
| Pulse Width Distortion, /tPLH − tPHL/ (BRW) | PWD | 3 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Change vs. Temperature (BRW) | 5 | ps/°C | CL = 15 pF, CMOS signal levels | 5 | |||
| Propagation Delay Skew (BRW) | tPSK | 15 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Channel-to-Channel Matching, Codirectional Channels (BRW) | tPSKCD | 3 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Channel-to-Channel Matching, Opposing-Directional Channels (BRW) | tPSKOD | 6 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Output Disable Propagation Delay (High/Low to High Impedance) | tPHZ, tPLH | 6 | 8 | ns | CL = 15 pF, CMOS signal levels | 5 | |
| Output Enable Propagation Delay (High Impedance to High/Low) | tPZH, tPZL | 6 | 8 | ns | CL = 15 pF, CMOS signal levels | 5 | |
| Output Rise/Fall Time (10% to 90%) | tR/tF | 2.5 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Common-Mode Transient Immunity at Logic High Output | /CMH/ | 25 | 35 | kV/µs | VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V | 5 | |
| Common-Mode Transient Immunity at Logic Low Output | /CML/ | 25 | 35 | kV/µs | VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V | 5 | |
| Input Supply Current per Channel, Quiescent (3 V) | IDDI (Q) | 0.26 | 0.31 | mA | 6 | ||
| Output Supply Current per Channel, Quiescent (3 V) | IDDO (Q) | 0.11 | 0.14 | mA | 6 | ||
| ADuM1402 VDD1 or VDD2 Supply Current, DC to 2 Mbps (3 V) | IDD1 (Q), IDD2 (Q) | 0.9 | 1.5 | mA | DC to 1 MHz logic signal freq. | 6 | |
| ADuM1402 VDD1 or VDD2 Supply Current, 10 Mbps (3 V) | IDD1 (10), IDD2 (10) | 3 | 4.2 | mA | 5 MHz logic signal freq. | 6 | |
| Input Currents (3 V) | IIA, IIB, IIC, IID, IE1, IE2 | -10 | 0.01 | 10 | µA | 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 | 6 |
| Logic High Input Threshold (3 V) | VIH, VEH | 1.6 | V | 6 | |||
| Logic Low Input Threshold (3 V) | VIL, VEL | 0.4 | V | 6 | |||
| Logic Low Output Voltages (3 V) | VOAL, VOBL, VOCL, VODL | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 6 | |
| Logic Low Output Voltages (3 V) | VOAL, VOBL, VOCL, VODL | 0.04 | 0.1 | V | IOx = 400 µA, VIx = VIxL | 6 | |
| Logic Low Output Voltages (3 V) | VOAL, VOBL, VOCL, VODL | 0.2 | 0.4 | V | IOx = 3.2 mA, VIx = VIxL | 6 | |
| Minimum Pulse Width (BRW, 3 V) | PW | 100 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Maximum Data Rate (BRW, 3 V) | 10 | Mbps | CL = 15 pF, CMOS signal levels | 7 | |||
| Propagation Delay (BRW, 3 V) | tPHL, tPLH | 20 | 38 | 50 | ns | CL = 15 pF, CMOS signal levels | 7 |
| Pulse Width Distortion, /tPLH − tPHL/ (BRW, 3 V) | PWD | 3 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Change vs. Temperature (BRW, 3 V) | 5 | ps/°C | CL = 15 pF, CMOS signal levels | 7 | |||
| Propagation Delay Skew (BRW, 3 V) | tPSK | 22 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Channel-to-Channel Matching, Codirectional Channels (BRW, 3 V) | tPSKCD | 3 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Channel-to-Channel Matching, Opposing-Directional Channels (BRW, 3 V) | tPSKOD | 6 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Output Disable Propagation Delay (High/Low to High Impedance) (3 V) | tPHZ, tPLH | 6 | 8 | ns | CL = 15 pF, CMOS signal levels | 7 | |
| Output Enable Propagation Delay (High Impedance to High/Low) (3 V) | tPZH, tPZL | 6 | 8 | ns | CL = 15 pF, CMOS signal levels | 7 | |
| Output Rise/Fall Time (10% to 90%) (3 V) | tR/tF | 3 | ns | CL = 15 pF, CMOS signal levels | 7 | ||
| Common-Mode Transient Immunity at Logic High Output (3 V) | /CMH/ | 25 | 35 | kV/µs | VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V | 7 | |
| Common-Mode Transient Immunity at Logic Low Output (3 V) | /CML/ | 25 | 35 | kV/µs | VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V | 7 | |
| Storage Temperature | TST | -65 | 150 | °C | 21 | ||
| Ambient Operating Temperature (grade 1) | TA | -40 | 105 | °C | Footnote 1: does not apply to ADuM1400W/ADuM1401W/ADuM1402W automotive grade versions | 21 | |
| Supply Voltages | VDD1, VDD2 | -0.5 | 7 | V | All voltages relative to their respective ground | 21 | |
| Input Voltage | VIA, VIB, VIC, VID, VE1, VE2 | -0.5 | V | Max: VDDI + 0.5 V | 21 | ||
| Output Voltage | VOA, VOB, VOC, VOD | -0.5 | V | Max: VDDO + 0.5 V | 21 | ||
| Average Output Current per Pin, Side 1 | IO1 | -18 | 18 | mA | 21 | ||
| Average Output Current per Pin, Side 2 | IO2 | -22 | 22 | mA | 21 | ||
| Common-Mode Transients | -100 | 100 | kV/µs | Across the insulation barrier | 21 | ||
| Operating Temperature (grade 1) | TA | -40 | 105 | °C | Footnote 1: does not apply to ADuM1400W/ADuM1401W/ADuM1402W automotive grade versions | 20 | |
| Supply Voltages | VDD1, VDD2 | 2.7 | 5.5 | V | Footnote 1: not for W automotive versions; all voltages relative to their respective ground | 20 | |
| Input Signal Rise and Fall Times | 1 | ms | 20 | ||||
| IC Junction to Case Thermal Resistance, Side 1 | θJCI | 33 | °C/W | Thermocouple located at center of package underside | 19 | ||
| IC Junction to Case Thermal Resistance, Side 2 | θJCO | 28 | °C/W | Thermocouple located at center of package underside | 19 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | 2 In accordance with DIN V VDE V 0884-10, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The | 19 |
CAD (KiCad official)
- Symbol:
ADUM1402BRWZ-RL - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
adum1402brwz-rl-etched.step/adum1402brwz-rl-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum1402brwz-rl.step/adum1402brwz-rl.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (31 pp, sha256
416fb6e11b4027f6, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).