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ADUM1401ARWZ

Analog Devices · Digital Isolators · SOIC-16-300mil

ADUM1401ARWZ from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, referenced to GND1.
2 GND1 power_in Ground reference for isolator side 1; pin 2 and pin 8 are internally connected and connecting both to GND1 is recommended.
3 VIA input Logic input A on isolator side 1.
4 VIB input Logic input B on isolator side 1.
5 VIC input Logic input C on isolator side 1.
6 VOD output Logic output D on isolator side 1; it is enabled when VE1 is high or disconnected and disabled when VE1 is low.
7 VE1 input Active high output enable for side 1; connecting VE1 to an external logic high or low is recommended in noisy environments.
8 GND1 power_in Ground reference for isolator side 1; internally connected to pin 2, and connecting both to GND1 is recommended.
9 GND2 power_in Ground reference for isolator side 2; pin 9 and pin 15 are internally connected and connecting both to GND2 is recommended.
10 VE2 input Active high output enable for side 2; VOA, VOB, and VOC are enabled when VE2 is high or disconnected and disabled when VE2 is low.
11 VID input Logic input D on isolator side 2.
12 VOC output Logic output C on isolator side 2.
13 VOB output Logic output B on isolator side 2.
14 VOA output Logic output A on isolator side 2.
15 GND2 power_in Ground reference for isolator side 2; internally connected to pin 9, and connecting both to GND2 is recommended.
16 VDD2 power_in Supply voltage for isolator side 2, referenced to GND2.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Supply Current per Channel, Quiescent (5 V, 105°C) IDDI (Q) 0.5 0.53 mA 4
Output Supply Current per Channel, Quiescent (5 V, 105°C) IDDO (Q) 0.19 0.21 mA 4
ADuM1401 VDD1 Supply Current (5 V, 105°C) IDD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal freq. 4
ADuM1401 VDD2 Supply Current (5 V, 105°C) IDD2 (Q) 1.2 1.8 mA DC to 1 MHz logic signal freq. 4
Input Currents (5 V, 105°C) IIA, IIB, IIC, IID, IE1, IE2 -10 0.01 10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 4
Logic High Input Threshold (5 V/3 V operation) VIH, VEH 2 V 4
Logic Low Input Threshold (5 V/3 V operation) VIL, VEL 0.8 V 4
Logic Low Output Voltage (5 V, 105°C) VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 µA, VIx = VIxL 4
Logic Low Output Voltage (5 V, 105°C) VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 4
Logic Low Output Voltage (5 V, 105°C) VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 3.2 mA, VIx = VIxL 4
Minimum Pulse Width (ADuM1401ARW grade, 5 V) PW 1000 ns CL = 15 pF, CMOS signal levels 4
Maximum Data Rate (ADuM1401ARW grade, 5 V) 1 Mbps CL = 15 pF, CMOS signal levels 4
Propagation Delay (ADuM1401ARW grade, 5 V) tPHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels 4
Pulse Width Distortion, /tPLH − tPHL/ (ARW grade, 5 V) PWD 40 ns CL = 15 pF, CMOS signal levels 5
Propagation Delay Skew (ARW grade, 5 V) tPSK 50 ns CL = 15 pF, CMOS signal levels 5
Channel-to-Channel Matching (ARW grade, 5 V) tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels 5
Output Disable Propagation Delay (High/Low to High Impedance, 5 V) tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels 5
Output Enable Propagation Delay (High Impedance to High/Low, 5 V) tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels 5
Output Rise/Fall Time (10% to 90%, 5 V) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels 5
Common-Mode Transient Immunity at Logic High Output (5 V, 105°C) /CMH/ 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 5
Common-Mode Transient Immunity at Logic Low Output (5 V, 105°C) /CML/ 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 5
Input Supply Current per Channel, Quiescent (3 V, 105°C) IDDI (Q) 0.26 0.31 mA 6
Output Supply Current per Channel, Quiescent (3 V, 105°C) IDDO (Q) 0.11 0.14 mA 6
ADuM1401 VDD1 Supply Current (3 V, 105°C) IDD1 (Q) 1 1.6 mA DC to 1 MHz logic signal freq. 6
ADuM1401 VDD2 Supply Current (3 V, 105°C) IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq. 6
Input Currents (3 V, 105°C) IIA, IIB, IIC, IID, IE1, IE2 -10 0.01 10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 6
Logic High Input Threshold (3 V/5 V or 3 V operation) VIH, VEH 1.6 V 6
Logic Low Input Threshold (3 V operation) VIL, VEL 0.4 V 6
Logic Low Output Voltage (3 V, 105°C) VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 µA, VIx = VIxL 6
Logic Low Output Voltage (3 V, 105°C) VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 6
Logic Low Output Voltage (3 V, 105°C) VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 3.2 mA, VIx = VIxL 6
Minimum Pulse Width (ADuM1401ARW grade, 3 V) PW 1000 ns CL = 15 pF, CMOS signal levels 7
Maximum Data Rate (ADuM1401ARW grade, 3 V) 1 Mbps CL = 15 pF, CMOS signal levels 7
Propagation Delay Skew (ARW grade, 3 V) tPSK 50 ns CL = 15 pF, CMOS signal levels 7
Channel-to-Channel Matching (ARW grade, 3 V) tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels 7
Output Disable Propagation Delay (High/Low to High Impedance, 3 V) tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels 7
Output Enable Propagation Delay (High Impedance to High/Low, 3 V) tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels 7
Output Rise/Fall Time (10% to 90%, 3 V) tR/tF 3 ns CL = 15 pF, CMOS signal levels 7
Common-Mode Transient Immunity at Logic High Output (3 V, 105°C) /CMH/ 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 7
Common-Mode Transient Immunity at Logic Low Output (3 V, 105°C) /CML/ 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 7
Operating Temperature (TA), 105°C grade TA -40 105 °C Option 1; does not apply to ADuM1400W/ADuM1401W/ADuM1402W automotive grade 20
Supply Voltages (VDD1, VDD2) VDD1, VDD2 2.7 5.5 V Option 1; relative to their respective ground 20
Input Signal Rise and Fall Times 1 ms 20
Storage Temperature TST -65 150 °C 21
Ambient Operating Temperature (105°C grade) TA -40 105 °C Option 1; does not apply to automotive grade versions 21
Supply Voltages VDD1, VDD2 -0.5 7 V Relative to their respective ground 21
Average Output Current per Pin, Side 1 IO1 -18 18 mA See Figure 4 for derating with temperature 21
Average Output Current per Pin, Side 2 IO2 -22 22 mA See Figure 4 for derating with temperature 21
Common-Mode Transients -100 100 kV/µs Common-mode transients across the insulation barrier 21
Logic High Output Voltage (5 V, 105°C), IOx = −20 µA VOAH, VOBH, VOCH, VODH 5 V IOx = −20 µA, VIx = VIxH 4
Logic High Output Voltage (5 V, 105°C), IOx = −3.2 mA VOAH, VOBH, VOCH, VODH 4.8 V IOx = −3.2 mA, VIx = VIxH 4
Logic High Output Voltage (3 V, 105°C), IOx = −20 µA VOAH, VOBH, VOCH, VODH 3 V IOx = −20 µA, VIx = VIxH 6
Logic High Output Voltage (3 V, 105°C), IOx = −3.2 mA VOAH, VOBH, VOCH, VODH 2.8 V IOx = −3.2 mA, VIx = VIxH 6
IC Junction to Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located at center of package underside 19
IC Junction to Case Thermal Resistance, Side 2 θJCO 28 °C/W Thermocouple located at center of package underside 19

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC 2 In accordance with DIN V VDE V 0884-10, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The 19

CAD (KiCad official)

  • Symbol: ADUM1401ARWZ
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: adum1401arwz-etched.step / adum1401arwz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1401arwz.step / adum1401arwz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (31 pp, sha256 416fb6e11b4027f6, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF