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ADUM1401ARWZ-RL

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Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADUM1401ARWZ-RL

Analog Devices · Digital Isolators · SOIC-16-300mil

ADUM1401ARWZ-RL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, recommended operating range 2.7 V to 5.5 V relative to GND1.
2 GND1 power_in Ground 1, the ground reference for isolator side 1; pins 2 and 8 are internally connected and connecting both to GND1 is recommended.
3 VIA input Logic input A on side 1; input voltage must stay between −0.5 V and VDDI + 0.5 V.
4 VIB input Logic input B on side 1; input voltage must stay between −0.5 V and VDDI + 0.5 V.
5 VIC input Logic input C on side 1; input voltage must stay between −0.5 V and VDDI + 0.5 V.
6 VOD tri_state Logic output D on side 1; enabled when VE1 is high or disconnected and disabled to high impedance when VE1 is low.
7 VE1 input Output enable 1, active-high input for VOD; connecting it to an external logic high or low is recommended in noisy environments.
8 GND1 power_in Ground 1, internally connected to pin 2; connecting both pins to GND1 is recommended.
9 GND2 power_in Ground 2, the ground reference for isolator side 2; internally connected to pin 15 and connecting both to GND2 is recommended.
10 VE2 input Output enable 2, active-high input for VOA, VOB and VOC; these outputs are disabled when VE2 is low and connecting VE2 to an external logic level is recommended in noisy environments.
11 VID input Logic input D on side 2; input voltage must stay between −0.5 V and VDDI + 0.5 V.
12 VOC tri_state Logic output C on side 2; enabled when VE2 is high or disconnected and high impedance when VE2 is low.
13 VOB tri_state Logic output B on side 2; enabled when VE2 is high or disconnected and high impedance when VE2 is low.
14 VOA tri_state Logic output A on side 2; enabled when VE2 is high or disconnected and high impedance when VE2 is low.
15 GND2 power_in Ground 2, the ground reference for isolator side 2; internally connected to pin 9 and connecting both to GND2 is recommended.
16 VDD2 power_in Supply voltage for isolator side 2, recommended operating range 2.7 V to 5.5 V relative to GND2.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature (TA), commercial grade (non-W) TA -40 105 °C 20
Supply Voltages (VDD1, VDD2), non-W grade VDD1, VDD2 2.7 5.5 V All voltages relative to their respective ground 20
Input Signal Rise and Fall Times 1 ms 20
Storage Temperature TST -65 150 °C 21
Ambient Operating Temperature, non-W grade TA -40 105 °C 21
Supply Voltages VDD1, VDD2 -0.5 7 V All voltages relative to their respective ground 21
Input Voltage (VIA, VIB, VIC, VID, VE1, VE2) VI -0.5 V Maximum printed as VDDI + 0.5 V 21
Output Voltage (VOA, VOB, VOC, VOD) VO -0.5 V Maximum printed as VDDO + 0.5 V 21
Average Output Current per Pin, Side 1 IO1 -18 18 mA 21
Average Output Current per Pin, Side 2 IO2 -22 22 mA 21
Common-Mode Transients -100 100 kV/µs Common-mode transients across the insulation barrier 21
IC Junction to Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located at center of package underside 19
IC Junction to Case Thermal Resistance, Side 2 θJCO 28 °C/W Thermocouple located at center of package underside 19
5 V, 105°C: Input Supply Current per Channel, Quiescent IDDI (Q) 0.5 0.53 mA 4
5 V, 105°C: Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.21 mA 4
5 V, 105°C: ADuM1401 VDD1 Supply Current, DC to 2 Mbps IDD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal freq. 4
5 V, 105°C: ADuM1401 VDD2 Supply Current, DC to 2 Mbps IDD2 (Q) 1.2 1.8 mA DC to 1 MHz logic signal freq. 4
5 V, 105°C: Input Currents IIA, IIB, IIC, IID, IE1, IE2 -10 0.01 10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 4
5 V, 105°C: Logic High Input Threshold VIH, VEH 2 V 4
5 V, 105°C: Logic Low Input Threshold VIL, VEL 0.8 V 4
5 V, 105°C: Logic High Output Voltage (VOAH, VOBH, VOCH, VODH) VOAH, VOBH, VOCH, VODH 5 V IOx = −20 µA, VIx = VIxH; printed min is (VDD1 or VDD2) − 0.1 V 4
5 V, 105°C: Logic High Output Voltage (VOAH, VOBH, VOCH, VODH) VOAH, VOBH, VOCH, VODH 4.8 V IOx = −3.2 mA, VIx = VIxH; printed min is (VDD1 or VDD2) − 0.4 V 4
5 V, 105°C: Logic Low Output Voltage (VOAL, VOBL, VOCL, VODL) VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 µA, VIx = VIxL 4
5 V, 105°C: Logic Low Output Voltage (VOAL, VOBL, VOCL, VODL) VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 4
5 V, 105°C: Logic Low Output Voltage (VOAL, VOBL, VOCL, VODL) VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 3.2 mA, VIx = VIxL 4
5 V, 105°C ARW grade: Minimum Pulse Width PW 1000 ns CL = 15 pF, CMOS signal levels 4
5 V, 105°C ARW grade: Maximum Data Rate 1 Mbps CL = 15 pF, CMOS signal levels 4
5 V, 105°C ARW grade: Propagation Delay tPHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels 4
5 V, 105°C ARW grade: Pulse Width Distortion PWD 40 ns CL = 15 pF, CMOS signal levels 5
5 V, 105°C ARW grade: Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels 5
5 V, 105°C ARW grade: Propagation Delay Skew tPSK 50 ns CL = 15 pF, CMOS signal levels 5
5 V, 105°C ARW grade: Channel-to-Channel Matching tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels 5
5 V, 105°C: Output Disable Propagation Delay (High/Low to High Impedance) tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels 5
5 V, 105°C: Output Enable Propagation Delay (High Impedance to High/Low) tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels 5
5 V, 105°C: Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels 5
5 V, 105°C: Common-Mode Transient Immunity at Logic High Output /CMH/ 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 5
5 V, 105°C: Common-Mode Transient Immunity at Logic Low Output /CML/ 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 5
5 V, 105°C: Refresh Rate fr 1.2 Mbps 5
3 V, 105°C: Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.31 mA 6
3 V, 105°C: Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.14 mA 6
3 V, 105°C: ADuM1401 VDD1 Supply Current, DC to 2 Mbps IDD1 (Q) 1 1.6 mA DC to 1 MHz logic signal freq. 6
3 V, 105°C: ADuM1401 VDD2 Supply Current, DC to 2 Mbps IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq. 6
3 V, 105°C: Input Currents IIA, IIB, IIC, IID, IE1, IE2 -10 0.01 10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 6
3 V, 105°C: Logic High Input Threshold VIH, VEH 1.6 V 6
3 V, 105°C: Logic Low Input Threshold VIL, VEL 0.4 V 6
3 V, 105°C: Logic High Output Voltage VOAH, VOBH, VOCH, VODH 3 V IOx = −20 µA, VIx = VIxH; printed min is (VDD1 or VDD2) − 0.1 V 6
3 V, 105°C: Logic High Output Voltage VOAH, VOBH, VOCH, VODH 2.8 V IOx = −3.2 mA, VIx = VIxH; printed min is (VDD1 or VDD2) − 0.4 V 6
3 V, 105°C: Logic Low Output Voltage VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 µA, VIx = VIxL 6
3 V, 105°C: Logic Low Output Voltage VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 6
3 V, 105°C: Logic Low Output Voltage VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 3.2 mA, VIx = VIxL 6
3 V, 105°C ARW grade: Minimum Pulse Width PW 1000 ns CL = 15 pF, CMOS signal levels 7
3 V, 105°C ARW grade: Maximum Data Rate 1 Mbps CL = 15 pF, CMOS signal levels 7
3 V, 105°C ARW grade: Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels 7
3 V, 105°C ARW grade: Propagation Delay Skew tPSK 50 ns CL = 15 pF, CMOS signal levels 7
3 V, 105°C ARW grade: Channel-to-Channel Matching tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels 7
3 V, 105°C: Output Disable Propagation Delay (High/Low to High Impedance) tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels 7
3 V, 105°C: Output Enable Propagation Delay (High Impedance to High/Low) tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels 7
3 V, 105°C: Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels 7
3 V, 105°C: Common-Mode Transient Immunity at Logic High Output /CMH/ 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 7
3 V, 105°C: Common-Mode Transient Immunity at Logic Low Output /CML/ 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 7
3 V, 105°C: Refresh Rate fr 1.1 Mbps 7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC 2 In accordance with DIN V VDE V 0884-10, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The 19

CAD (KiCad official)

  • Symbol: ADUM1401ARWZ-RL
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: adum1401arwz-rl-etched.step / adum1401arwz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1401arwz-rl.step / adum1401arwz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (31 pp, sha256 416fb6e11b4027f6, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF